公开(公告)号：DE69609283D1

公开(公告)日：2000-08-17

申请号：DE69609283

申请日：1996-10-25

Applicant: SIEMENS AG ,  IBM

Inventor： PESCHKE MATTHIAS L ,  GAMBINO JEFFREY ,  RYAN JAMES GARDNER ,  STENGL REINHARD JOHANNES

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/60

Abstract: A method of fabricating a self-aligned borderless contact in a semiconductor device. The semiconductor device includes a first conductor level, a patterned conductor level defining a pair of spaced apart conducting segments, and a dielectric insulating layer disposed between the first conductor level and the patterned conductor level, and over the pair of spaced apart conducting segments of the patterned conductor level. The method comprises the steps of etching a contact hole in a selected region of the dielectric insulating layer which lies above and is substantially aligned between the pair of the segments. The etching continues through the dielectric insulating layer so that a portion of the dielectric insulating layer remains between the contact hole and the first conductor level. A spacer is formed which lines the contact hole. The remaining portion of the insulating layer which extends between the contact hole and the first conductor level is then etched to extend the contact hole to the first conductor level. The spacer substantially prevents the erosion of the pair of spaced apart segments during the etching of the remaining portion of the insulating layer. The contact hole is then filled with a conductive material to form the self-aligned borderless contact. The borderless contact formed by the present method is electrically isolated from the pair of spaced apart conducting segments of the patterned conductor level by the dielectric insulating layer.

公开(公告)号：JPH11177045A

公开(公告)日：1999-07-02

申请号：JP27902198

申请日：1998-09-30

Applicant: SIEMENS AG

Inventor： SCHELLER GERD ,  GALL MARTIN ,  STENGL REINHARD JOHANNES

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To create a memory cell with creative and new structure, by forming a trench on one conductivity silicon chip, forming a dielectric layer over a wall of a trench, filling the trench, and performing epitaxial growth of a silicon layer over the surface of the chip. SOLUTION: A trench 22 is filled with n+ type polycrystal silicon 23 being doped with a high concentration that is used as the accumulation node of, for example, a memory cell 11. Also, essentially, a single crystal middle region 30 is provided between the polycrystal fill 23 of the trench 22 and a silicon layer 34 at the upper portion of the region 30. The polycrystal fill 23 of the trench 22 is used as one source/drain of a switching transistor and the silicon layer 34 is used as the other source/drain of the switching transistor. Also, the middle region 30 has high mobility for a charged carrier in an NMOS transistor due to a relatively high switching speed.