公开(公告)号：KR101167530B1

公开(公告)日：2012-07-20

申请号：KR20120001306

申请日：2012-01-05

Applicant: SIGETRONICS INC

Inventor： SHIM KYU HWAN ,  CHO DEOK HO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7802 ,  H01L29/1045 ,  H01L29/1054

Abstract: PURPOSE: A super hetero-junction semiconductor device and a manufacturing method thereof are provided to regularly control impurity concentration filler by minimizing co-doping between p-filler and n-filler due to inter-diffusion. CONSTITUTION: A first conductive type silicon semiconductor substrate doped to high concentration is prepared. A first conductive epitaxial layer is formed at the upper side of the first conductive type silicon semiconductor substrate. A plurality of first conductive type fillers is formed by etching the first conductive epitaxial layer as a predetermined distance. A plurality of second conductive type fillers is composed of a SiGe single epitaxial layer having a single composition or a plurality of SiGe single epitaxial layers having a plurality of compositions in order to prevent co-doping of impurities.

Abstract translation: 目的：提供超异质结半导体器件及其制造方法，以通过最小化由互扩散引起的p-填料和n-填料之间的共掺杂来规则地控制杂质浓度填料。 构成：制备掺杂高浓度的第一导电型硅半导体衬底。 第一导电外延层形成在第一导电型硅半导体衬底的上侧。 通过将第一导电外延层蚀刻为预定距离来形成多个第一导电型填料。 多个第二导电型填料由具有单一组成的SiGe单一外延层或具有多个组成的多个SiGe单一外延层组成，以防止杂质的共掺杂。