公开(公告)号：WO2014051511A2

公开(公告)日：2014-04-03

申请号：PCT/SE2013051124

申请日：2013-09-27

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KNUTSSON HENRIK

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to methods of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface. It comprises providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited Cu on the Ni by a plating process. Line widths and spacings

Abstract translation: 本发明涉及制造半导体衬底中具有高纵横比的衬底贯穿金属通孔和衬底表面上的金属图案的方法。 它包括提供半导体衬底（晶片）并在衬底上沉积多晶硅。 通过蚀刻掉不需要的部分来图案化衬底表面上的多晶硅。 然后，通过无电处理将Ni选择性地沉积在多晶硅上。 穿过基板形成通孔，其中孔中的壁受到与上述相同的处理。 通过电镀工艺将Cu沉积在Ni上。 晶圆两侧的线宽和间距<10μm。

公开(公告)号：SE538062C2

公开(公告)日：2016-02-23

申请号：SE1251089

申请日：2012-09-27

Applicant: SILEX MICROSYSTEMS AB

Inventor： KNUTSSON HENRIK ,  EBEFORS THORBJÖRN

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/52

公开(公告)号：HK1213089A1

公开(公告)日：2016-06-24

申请号：HK16100996

申请日：2016-01-29

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJRN ,  KNUTSSON HENRIK

IPC: H01L20060101

公开(公告)号：SE1251089A1

公开(公告)日：2014-03-28

申请号：SE1251089

申请日：2012-09-27

Applicant: SILEX MICROSYSTEMS AB

Inventor： KNUTSSON HENRIK ,  EBEFORS THORBJÖRN

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/52

公开(公告)号：EP2901475A4

公开(公告)日：2016-05-04

申请号：EP13841291

申请日：2013-09-27

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJÖRN ,  KNUTSSON HENRIK

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings