公开(公告)号：US20180159800A1

公开(公告)日：2018-06-07

申请号：US15370508

申请日：2016-12-06

Applicant: Silicon Graphics International Corp.

Inventor： Joseph G. Tietz ,  Eric C. Fromm

IPC: H04L12/937 ,  H04L29/06 ,  H04L29/08 ,  H04L12/833 ,  H04L12/26

Abstract: This patent application relates generally to an age-based arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), in which age-based determinations are performed at the input sources of the data streams in order to designate certain packets as high-priority packets based on packet ages, and the destination expedites processing of the high-priority packets. Among other things, this approach offloads the age-based determinations from the destination, where they otherwise can cause delays in processing packets.

公开(公告)号：US20180159799A1

公开(公告)日：2018-06-07

申请号：US15370485

申请日：2016-12-06

Applicant: Silicon Graphics International Corp.

Inventor： Joseph G. Tietz ,  Eric C. Fromm

IPC: H04L12/937

CPC classification number: H04L49/254

Abstract: This patent application relates generally to a predictive arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), where each data stream is associated with a number of sources competing for the shared resource, and the destination provides access to the shared resource based on the number of sources competing for the shared resource rather than just on the number of data streams. Among other things, this approach can more fairly distribute access to the shared resource among the competing sources.

公开(公告)号：US09104343B2

公开(公告)日：2015-08-11

申请号：US13798604

申请日：2013-03-13

Applicant: Silicon Graphics International Corp.

Inventor： Rodney A. Ruesch ,  Eric C. Fromm ,  Robert W. Cutler ,  Richard G. Finstad ,  Dale R. Purdy ,  Brian J. Johnson ,  John F. Steiner

IPC: G06F1/08 ,  H04J3/06

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  H04J3/0638 ,  H04J3/0661

Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

Abstract translation: 为HPC系统中的每个处理器生成处理器时钟信号，使得所有处理器时钟信号具有相同的频率。 此外，作为启动（启动）过程的一部分，进程设置处理器的所有时间戳计数器（TSC），这样它们表示相同的时间。 HPC系统的每个刀片从同步通信网络恢复恢复的时钟信号，刀片耦合到同步通信网络。 刀片从恢复的时钟信号产生处理器时钟，并将处理器时钟提供给刀片上的处理器。 每个机箱耦合到第二个系统级的同步通信网络，每个机箱将其机箱同步通信网络与全系统的同步通信系统同步。 因此，所有处理器时钟信号都以相同的频率生成。

公开(公告)号：US20140269324A1

公开(公告)日：2014-09-18

申请号：US13830432

申请日：2013-03-14

Applicant: SILICON GRAPHICS INTERNATIONAL CORP

Inventor： Joseph George Tietz ,  Gregory Michael Thorson ,  Eric C. Fromm

IPC: H04L12/803 ,  H04L12/721

CPC classification number: H04L45/28 ,  H04L45/22 ,  H04L45/70 ,  H04L47/122

Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.

Abstract translation: 自适应路由器预测可能的未来拥塞，并且能够在拥塞发生之前选择替代路由，从而避免拥塞。 自适应路由器可以使用主路由，直到它预测将发生拥塞。 自适应路由器在主网络接口上测量数据包流量，如flit volume，以预测拥塞。 自适应路由器在拖尾时间段内保持由主网络接口处理的飞行数量的拖尾和。 如果总和超过阈值，则自适应路由器假定路由将变得拥塞，并且自适应路由器能够考虑在可能的次路由上路由将来的分组，或至少当前分组。

公开(公告)号：US20140250252A1

公开(公告)日：2014-09-04

申请号：US13784160

申请日：2013-03-04

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Eric C. Fromm

IPC: G06F5/06 ,  G06F13/16

CPC classification number: G06F5/065 ,  G06F13/1689

Abstract: A modular first-in first-out circuit including at least three non-addressable memory blocks forming a data pipeline is disclosed. At least two of the memory block including a data storage structure for receiving as input data from a global data bus and a control logic structure including logic for determining whether data should be added to the data storage structure from the global data bus and whether any data within the data storage structure should be transferred to the output of the memory block. The data storage structure of the at least two memory blocks includes a first data input for selectively receiving data from the global data bus and a second data input for selectively receiving data from a previous memory block in the modular first-in first-out circuit.

Abstract translation: 公开了包括形成数据流水线的至少三个不可寻址存储块的模块化先进先出电路。 所述存储块中的至少两个包括用于从全局数据总线接收作为输入数据的数据存储结构以及包括用于确定是否应将数据从全局数据总线添加到数据存储结构的逻辑的控制逻辑结构以及是否有任何数据 在数据存储结构中应该传输到内存块的输出。 所述至少两个存储器块的数据存储结构包括用于选择性地从全局数据总线接收数据的第一数据输入和用于从模块化先进先出电路中的先前存储块选择性地接收数据的第二数据输入。

公开(公告)号：US20140281656A1

公开(公告)日：2014-09-18

申请号：US13798604

申请日：2013-03-13

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Rodney A. Ruesch ,  Eric C. Fromm ,  Robert W. Cutler ,  Richard G. Finstad ,  Dale R. Purdy ,  Brian J. Johnson ,  John F. Steiner

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  H04J3/0638 ,  H04J3/0661

Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

Abstract translation: 为HPC系统中的每个处理器生成处理器时钟信号，使得所有处理器时钟信号具有相同的频率。 此外，作为启动（启动）过程的一部分，进程设置处理器的所有时间戳计数器（TSC），这样它们表示相同的时间。 HPC系统的每个刀片从同步通信网络恢复恢复的时钟信号，刀片耦合到同步通信网络。 刀片从恢复的时钟信号产生处理器时钟，并将处理器时钟提供给刀片上的处理器。 每个机箱耦合到第二个系统级的同步通信网络，每个机箱将其机箱同步通信网络与全系统的同步通信系统同步。 因此，所有处理器时钟信号都以相同的频率生成。

公开(公告)号：US20140281208A1

公开(公告)日：2014-09-18

申请号：US13802086

申请日：2013-03-13

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Eric C. Fromm

IPC: G06F17/30

CPC classification number: G06F16/90339 ,  G11C15/04

Abstract: An associative look-up instruction for an instruction set architecture (ISA) of a processor and methods for use of an associative look-up instruction. The associative look-up instruction of the ISA specifies one or more fields within a data unit that are used as a pattern of bits for identifying data content in a memory structure to be loaded into hardware registers or other storage components of the ISA. Specified parameters of the associative operation may be explicit within the instruction or indirectly pointed to via hardware registers or other storage components of the ISA. The memory structure may be content addressable memory (CAM).

Abstract translation: 用于处理器的指令集架构（ISA）的关联查找指令以及使用关联查找指令的方法。 ISA的关联查找指令指定数据单元内的一个或多个字段，其用作用于识别要加载到ISA的硬件寄存器或其他存储组件的存储器结构中的数据内容的位模式。 关联操作的指定参数可以在指令内显式，也可以通过ISA的硬件寄存器或其他存储组件间接指出。 存储器结构可以是内容可寻址存储器（CAM）。

公开(公告)号：US09237093B2

公开(公告)日：2016-01-12

申请号：US13830432

申请日：2013-03-14

Applicant: Silicon Graphics International Corp.

Inventor： Joseph George Tietz ,  Gregory Michael Thorson ,  Eric C. Fromm

IPC: H04L12/721 ,  H04L12/703 ,  H04L12/803 ,  H04L12/707

CPC classification number: H04L45/28 ,  H04L45/22 ,  H04L45/70 ,  H04L47/122

Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.

Abstract translation: 自适应路由器预测可能的未来拥塞，并且能够在拥塞发生之前选择替代路由，从而避免拥塞。 自适应路由器可以使用主路由，直到它预测将发生拥塞。 自适应路由器在主网络接口上测量数据包流量，如flit volume，以预测拥塞。 自适应路由器在拖尾时间段内保持由主网络接口处理的飞行数量的拖尾和。 如果总和超过阈值，则自适应路由器假定路由将变得拥塞，并且自适应路由器能够考虑在可能的次路由上路由将来的分组，或至少当前分组。