公开(公告)号：DE69419339T2

公开(公告)日：2000-01-27

申请号：DE69419339

申请日：1994-03-30

Applicant: SONY CORP

Inventor： ARAKAWA HIDEKI ,  TANAKA AKIRA ,  ARASE KENSHIRO ,  MIYASHITA MASARU

IPC: G11C17/00 ,  G11C7/18 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  G11C7/00 ,  G11C16/06

Abstract: A non-volatile memory device including a plurality of block, each including: a main bit line; a plurality of sub-bit lines to which memory transistors are connected and which are arranged in parallel with respect to the main bit line; and two cascade-connected selection gates which are provided between the main bit line and sub-bit lines and which selectively connect the sub-bit lines.

公开(公告)号：DE69419339D1

公开(公告)日：1999-08-12

申请号：DE69419339

申请日：1994-03-30

Applicant: SONY CORP

Inventor： ARAKAWA HIDEKI ,  TANAKA AKIRA ,  ARASE KENSHIRO ,  MIYASHITA MASARU

IPC: G11C17/00 ,  G11C7/18 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  G11C7/00 ,  G11C16/06

Abstract: A non-volatile memory device including a plurality of block, each including: a main bit line; a plurality of sub-bit lines to which memory transistors are connected and which are arranged in parallel with respect to the main bit line; and two cascade-connected selection gates which are provided between the main bit line and sub-bit lines and which selectively connect the sub-bit lines.

公开(公告)号：DE69429567T2

公开(公告)日：2002-09-12

申请号：DE69429567

申请日：1994-10-14

Applicant: SONY CORP

Inventor： ARASE KENSHIRO ,  MAARI KOICHI

IPC: G11C16/34 ,  H01L21/8247 ,  H01L27/115

Abstract: In a flash type EEPROM device, when a dose amount of an impurity of a floating gate (FG/8) is controlled, or, a channel of a transistor (4) is buried by an ion implantation, the threshold value at no charges accumulated is set between the respective thresholds corresponding to data "0" and data "1" states, to reduce the disturbances of a drain and a gate when reading.

公开(公告)号：DE69429567D1

公开(公告)日：2002-02-07

申请号：DE69429567

申请日：1994-10-14

Applicant: SONY CORP

Inventor： ARASE KENSHIRO ,  MAARI KOICHI

IPC: G11C16/34 ,  H01L21/8247 ,  H01L27/115

Abstract: In a flash type EEPROM device, when a dose amount of an impurity of a floating gate (FG/8) is controlled, or, a channel of a transistor (4) is buried by an ion implantation, the threshold value at no charges accumulated is set between the respective thresholds corresponding to data "0" and data "1" states, to reduce the disturbances of a drain and a gate when reading.