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公开(公告)号：DE69226248T2
公开(公告)日：1998-11-26
申请号：DE69226248
申请日：1992-12-21
Applicant: SONY CORP
Inventor： TANAKA YUTAKA , FUJISHIRO SHIGEO
IPC: H04N19/50 , G06T7/20 , H04N5/14 , H04N19/423 , H04N19/51 , H04N19/543 , H04N19/587 , H04N19/59 , H04N19/80 , H04N19/85
Abstract: A motion detection signal delivered from a mixer (8) is output through a series circuit of a maximum value calculation portion (16) and a minimum value calculation portion (23). In each of the calculation portions (16, 23), calculation is performed within a block of 3-dot x 3-line. Missing of motion detection is prevented from occurring in the maximum value calculation portion (16) because the motion detection signal of the pixel under attention is calculated therein with the values within the block and, accordingly, the motion detection signal is expanded in the horizontal and vertical directions. A detection spread to a still picture portion occurring in the calculation portion is suppressed in the minimum value calculation portion (23) because, when surrounding motion detection signals therein are lower than the motion detection signal of the pixel under attention, the motion detection signal of the pixel under attention is replaced with the lower value. With the described arrangement, the missing of motion detection is advantageously prevented without inviting the detection spread to a still picture portion.
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公开(公告)号：DE69226248D1
公开(公告)日：1998-08-20
申请号：DE69226248
申请日：1992-12-21
Applicant: SONY CORP
Inventor： TANAKA YUTAKA , FUJISHIRO SHIGEO
IPC: H04N19/50 , G06T7/20 , H04N5/14 , H04N19/423 , H04N19/51 , H04N19/543 , H04N19/587 , H04N19/59 , H04N19/80 , H04N19/85
Abstract: A motion detection signal delivered from a mixer (8) is output through a series circuit of a maximum value calculation portion (16) and a minimum value calculation portion (23). In each of the calculation portions (16, 23), calculation is performed within a block of 3-dot x 3-line. Missing of motion detection is prevented from occurring in the maximum value calculation portion (16) because the motion detection signal of the pixel under attention is calculated therein with the values within the block and, accordingly, the motion detection signal is expanded in the horizontal and vertical directions. A detection spread to a still picture portion occurring in the calculation portion is suppressed in the minimum value calculation portion (23) because, when surrounding motion detection signals therein are lower than the motion detection signal of the pixel under attention, the motion detection signal of the pixel under attention is replaced with the lower value. With the described arrangement, the missing of motion detection is advantageously prevented without inviting the detection spread to a still picture portion.
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公开(公告)号：CA2485723A1
公开(公告)日：2005-04-22
申请号：CA2485723
申请日：2004-10-21
Applicant: SONY CORP
Inventor： FUJISHIRO SHIGEO , SOMEYA IKUO
Abstract: Disclosed herein is a data processing apparatus for converting discrete first data into second data having a different number of sampling data from the first data, including generating means for generating a plurality of the second data from the first data, first virtualizing means for generating first virtual data including a virtual succession of the first data, second virtualizing means for generating second virtual data including a virtual succession of each of the plural second data, error calculating means for calculating an error between each of the second virtual data with respect to the plural second data and the first virtual data, and selecting means for selecting either one of the plural second data based on the error.
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公开(公告)号：EP1014726A4
公开(公告)日：2001-05-09
申请号：EP99926833
申请日：1999-06-29
Applicant: SONY CORP
Inventor： UEHARA KENJI , MURAKAMI YOSHIHIRO , FUNADO SHIGETO , MATSUNAGA OSAMU , FUJISHIRO SHIGEO
IPC: H04N19/119 , H04N19/132 , H04N19/139 , H04N19/149 , H04N19/177 , H04N19/196 , H04N19/423 , H04N19/50 , H04N19/51 , H04N19/59 , H04N19/61 , H04N19/625 , H04N19/85 , H04N19/91 , H04N19/94 , H04N7/32 , H04N7/26 , H04N7/36 , H04N7/46 , H04N7/50
CPC classification number: H04N19/59 , H04N19/105 , H04N19/117 , H04N19/124 , H04N19/139 , H04N19/149 , H04N19/152 , H04N19/172 , H04N19/176 , H04N19/182 , H04N19/50 , H04N19/51 , H04N19/61 , H04N19/80
Abstract: An encoder in which a video signal is subjected to signal processing by a signal processing circuit and to motion compensation, differential data generated by the motion compensation is subjected to orthogonal transformation to generated coefficient data, encoded data is generated by quantizing the coefficient data, and the quantization step size for quantization is changed according to the amount of encoded data generated, the signal processing circuit being provided with moving vector detecting means for detecting a moving vector of the video signal, motion vector amount-of-codes measuring means for calculating the amount of codes of the moving vector based on the moving vector, coefficient data number-of-codes measuring means for measuring the amount of codes of the coefficient data, and number-of-pixels changing means for changing the number of pixels of the video signal according to the amount of codes of the moving vector and the amount of codes of the coefficient data.
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公开(公告)号：JP2000050283A
公开(公告)日：2000-02-18
申请号：JP21117698
申请日：1998-07-27
Applicant: SONY CORP
Inventor： FUJISHIRO SHIGEO , MATSUNAGA OSAMU
IPC: H04N19/50 , H04N7/01 , H04N19/105 , H04N19/126 , H04N19/139 , H04N19/182 , H04N19/196 , H04N19/20 , H04N19/423 , H04N19/46 , H04N19/503 , H04N19/51 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/80 , H04N19/85 , H04N19/91 , H04N7/32
Abstract: PROBLEM TO BE SOLVED: To reduce the generated code value of the motion vector that is caused, when the motion compensation processing is carried out by a coding means and to effectively code the video data, while preventing the image deterioration by applying the 1st pixel number conversion processing with respect to the video data in response to the moved variable of an image. SOLUTION: A video coding device 10 detects the moved variable of an image decided, based on the video data D10 via a moved variable detecting circuit 13 in every prescribed number of frames. When the detected moved variable is larger than a prescribed threshold, a coding part 17 compresses and codes the pixel number coverted video data D13 obtained via a pixel number converting circuit 16, by reducing horizontal pixel number M2 down to horizontal pixel number N2 for the data D10. Thus, the generated code value of a motion vector can be reduced to N2/M2 times. As a result, the quantization step size is reduced, and the deterioration of resolution can be suppressed in a DCT space, when for example the variable length coding data D22 are outputted at a fixed bit rate.
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Patent Agency Ranking
公开(公告)号：JPH10285559A
公开(公告)日：1998-10-23
申请号：JP8905697
申请日：1997-04-08
Applicant: SONY CORP
Inventor： MATSUNAGA OSAMU , FUJISHIRO SHIGEO , SHIOMOTO SHOJI , KOBAYASHI NAOMASA
IPC: H04N7/01
Abstract: PROBLEM TO BE SOLVED: To convert the video signal and the synchronizing signal of the interlace and progressive video information and synchronizing signal mutually by converting interlace synchronizing signals whose scanning line number is N into progressive synchronizing signals of N/2 lines or converting progressing synchronizing signals whose scanning line number is M into interlace synchronizing signals whose scanning line number is M/2 corresponding to control information. SOLUTION: A synchronizing signal conversion circuit 12 converts interlace synchronizing signals whose scanning line number is N into progressive synchronizing signals whose scanning line number is N/2 in the case of a control signal set to '0', and the circuit 12 converts progressive synchronizing signals whose scanning line number is M into interlace synchronizing signals whose scanning line number is M/2 in the case of a control signal set to '1', and then conducts no conversion in the case of a control signal set to '2'. For example, the circuit 12 converts received interlace synchronizing signals whose scanning line number is 1125 into progressing synchronizing signals whose scanning line number is 562 or 563 in the case of the control signal set to '0'.
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公开(公告)号：JPH08265662A
公开(公告)日：1996-10-11
申请号：JP6814995
申请日：1995-03-27
Applicant: SONY CORP
Inventor： FUJISHIRO SHIGEO , SADANAKA NOBUYUKI
Abstract: PURPOSE: To display a screen on which viewers' interests and producers' intentions are reflected. CONSTITUTION: An STDV signal decoded by decoders 6 to 9 are fed to picture element conversion circuits 10 to 13 in which conversion of picture elements such as magnification and reduction of an image is conducted and the result is fed to a synthesis circuit 15. The SVTD signal from the conversion circuits 10 to 13 is synthesized according to a control signal from a control circuit 4. Furthermore, a transmitter side display control signal included in header information or the like in coded data separated by a separate circuit 5 is fed to the control circuit 4 and the transmitter side display control signal and a receiver side display control signal formed in the receiver side fed through, e.g. an input terminal 3 are selected and the conversion of picture element number in the conversion circuits 10 to 13 and the synthesis in the synthesis circuit 15 are conducted according to the selected transmitter side or receiver side display control signal. The synthesized digital signal is fed to a D/A converter circuit 16 and a converted analog signal is extracted at an output terminal 17.
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8.发明专利
公开(公告)号：JPH07298094A
公开(公告)日：1995-11-10
申请号：JP9120294
申请日：1994-04-28
Applicant: SONY CORP
Inventor： FUJISHIRO SHIGEO
Abstract: PURPOSE:To improve the limit characteristic or passing characteristic of a horizontal frequency signal of a television signal. CONSTITUTION:A delay circuit D1 (D21, D41, D61) is arranged to an input part of (2n-1)th filter cells 2a, 2c, 2e, 2g respectively and no delay circuit is arranged to an input part of 2nth filter cells 2b, 2d, 2f, where n denotes positive integers. Thus, a line offset is provided. Line memories 1b-1g are arranged to a pre-stage of the filter cells 2b-2g and signals delayed by one line each sequentially are fed to the filter cells 2a-2g. An adder SA100 adds outputs of the filter cells 2a-2g and an output of a center tap multiplier M70 to provide an output of a signal.
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公开(公告)号：JPH04346586A
公开(公告)日：1992-12-02
申请号：JP14821891
申请日：1991-05-24
Applicant: SONY CORP
Inventor： FUJISHIRO SHIGEO
Abstract: PURPOSE:To obtain a VTR, which can simultaneously record/reproduce the NTSC signals of four systems or the MUSE signals of two systems, by providing a pseudo high-vision signal transforming means at an input step and providing a pseudo high-vision signal inverting means at an output step. CONSTITUTION:In the case of recording signals, a recording/reproducing processing part 1 executes a prescribed processing to signals inputted from a high fidelity signal input terminal 2 through a switch 3 and records those signals in a tape. In the case of reproducing, the signals are passed through a switch 4 and outputted from a high-vision signal output terminal 5. The input step is provided with pseudo high-vision signal transforming means 11A-14D so as to execute time division multiplexing to the NTSC video signals of four systems or the MUSE signals of two system, to transform those signals to pseudo high-vision signals and to supply them to the recording/reproducing processing part 1. The output step is provided with pseudo high-vision signal inverting means 21A-24F so as to transform the supplied pseudo high-vision signals to the NTSC signals of four systems or the MUSE signals of two systems and to output them. Thus, the recording area of the tape can be effectively utilized.
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公开(公告)号：JP2014123787A
公开(公告)日：2014-07-03
申请号：JP2012277561
申请日：2012-12-20
Inventor： FUJISHIRO SHIGEO , SUZUKI SADAHITO , KOSEKI HIDEYORI , TAKAHASHI NORIHIRO , FUJIWARA TAKAYOSHI
CPC classification number: H04N7/0135 , G06T3/4007 , H04N7/0132 , H04N7/014
Abstract: PROBLEM TO BE SOLVED: To improve image quality of a moving image whose frame rate is converted.SOLUTION: A normal interpolation image generating section generates an image to be interpolated between a plurality of original images reproduced along a time sequence as a normal interpolation image on the basis of the plurality of original images. A high frequency area extraction section extracts a high frequency area being an area whose spatial frequency is higher than a prescribed value in each of the plurality of original images. A high frequency area interpolation image generating section generates an image to be interpolated between the plurality of original images as a high frequency area interpolation image on the basis of a change of a position of the high frequency area with lapse of time on the time sequence and each of the plurality of original images. A synthesis section performs synthesis processing for synthesizing the normal interpolation image and the high frequency area interpolation image.
Abstract translation: 要解决的问题：提高帧速率被转换的运动图像的图像质量。解决方案：普通内插图像生成部分生成沿着时间序列再现的多个原始图像之间内插的图像作为正常内插图像 多个原始图像的基础。 高频区域提取部分提取在多个原始图像的每一个中空间频率高于规定值的区域的高频区域。 高频区域插值图像生成部基于时间序列上的高频区域的位置随时间的变化而在多个原始图像之间生成要插值的图像作为高频区域插值图像，以及 多个原始图像中的每一个。 合成部分执行用于合成正常内插图像和高频区域插值图像的合成处理。
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