公开(公告)号：DE3486471T2

公开(公告)日：1999-09-02

申请号：DE3486471

申请日：1984-12-19

Applicant: SONY CORP

Inventor： OZAKI SHINYA ,  ODAKA KENTARO ,  FUKAMI TADASHI

IPC: H03M20060101 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

Abstract: In method for decoding error correction code in which a first correction code of (n1, k1) (where n1 denotes the code length) is encoded for every k1 information symbols arranged in each column and a second error correction code of (n2, k2) (where n2 denotes the code length) are encoded for every k2 information symbols arranged in each row of a two dimentional arrangement of (k1 X k2), a first pointer formed by decoding the first error correction code is stored in a memory having n2 bits, a second pointer formed by decoding the second error correction code is stored in a memory having k2 bits. When the second error correction code is decoded, an erasure correction is made with respect to each of the code series of the second error correction code by employing the first pointer and a part of the calculation for obtaining an error value in this erasure correction may be carried out only once with respect to each of the code series of the second error correction code.

公开(公告)号：DE3486471D1

公开(公告)日：1999-04-15

申请号：DE3486471

申请日：1984-12-19

Applicant: SONY CORP

Inventor： OZAKI SHINYA ,  ODAKA KENTARO ,  FUKAMI TADASHI

IPC: H03M20060101 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

Abstract: In method for decoding error correction code in which a first correction code of (n1, k1) (where n1 denotes the code length) is encoded for every k1 information symbols arranged in each column and a second error correction code of (n2, k2) (where n2 denotes the code length) are encoded for every k2 information symbols arranged in each row of a two dimentional arrangement of (k1 X k2), a first pointer formed by decoding the first error correction code is stored in a memory having n2 bits, a second pointer formed by decoding the second error correction code is stored in a memory having k2 bits. When the second error correction code is decoded, an erasure correction is made with respect to each of the code series of the second error correction code by employing the first pointer and a part of the calculation for obtaining an error value in this erasure correction may be carried out only once with respect to each of the code series of the second error correction code.

公开(公告)号：AT177570T

公开(公告)日：1999-03-15

申请号：AT91200210

申请日：1984-12-19

Applicant: SONY CORP

Inventor： OZAKI SHINYA ,  ODAKA KENTARO ,  FUKAMI TADASHI

IPC: H03M20060101 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

Abstract: In method for decoding error correction code in which a first correction code of (n1, k1) (where n1 denotes the code length) is encoded for every k1 information symbols arranged in each column and a second error correction code of (n2, k2) (where n2 denotes the code length) are encoded for every k2 information symbols arranged in each row of a two dimentional arrangement of (k1 X k2), a first pointer formed by decoding the first error correction code is stored in a memory having n2 bits, a second pointer formed by decoding the second error correction code is stored in a memory having k2 bits. When the second error correction code is decoded, an erasure correction is made with respect to each of the code series of the second error correction code by employing the first pointer and a part of the calculation for obtaining an error value in this erasure correction may be carried out only once with respect to each of the code series of the second error correction code.

公开(公告)号：DE69032261T2

公开(公告)日：1998-12-03

申请号：DE69032261

申请日：1990-11-20

Applicant: SONY CORP

Inventor： FUKAMI TADASHI ,  YAMADA MAKOTO ,  KAJIWARA TSUTOMU

IPC: G11B15/18 ,  G11B20/10 ,  G11B27/032 ,  G11B27/036 ,  G11B27/10 ,  G11B27/30 ,  G11B5/008

Abstract: A digital signal processing circuit (8) for processing and recording data at various selectable rates, having an input/output circuit (40, 41) for receiving and outputting a digital signal; a recording circuit for generating a recording signal based on a digital signal received by the data signal processing circuit; a playback circuit (48) for retrieving recorded data; and a demodulation circuit for demodulating retrieved data. The processing and recording rates are determined by control data supplied to the circuit either via an operator or from a recorded signal.

公开(公告)号：DE69026922T2

公开(公告)日：1996-11-28

申请号：DE69026922

申请日：1990-10-24

Applicant: SONY CORP

Inventor： FUKAMI TADASHI ,  KAJIWARA TSUTOMU

IPC: G11B20/10 ,  G11B20/18

Abstract: A digital signal processing circuit has a memory circuit (44) to store reproduced data and recording information, a reproduced signal processing circuit (8) for demodulating a reproduced signal thereby to obtain the reproduction data and the recording information and for storing the reproduced data and the recording information in the memory circuit (44), an error detecting and correcting circuit (56) for executing an error detecting and correcting process on the reproduced data, and a data output circuit (72) for outputting the reproduced data stored in the memory circuit (44) on the basis of the recording information. The digital signal processing circuit (72 - Figure 3) incorporates a plurality of multiplex coincidence detecting circuits (78, 79, 80) for sequentially detecting whether the recording information coincides or not and for supplying the recording information, in which the coincidence result is respectively obtained a predetermined number of times, to the memory circuit (44); and a selecting circuit (76) for selectively supplying the recording information to the plurality of multiplex coincidence detecting circuits (78, 79, 80) in accordance with the kind of recording information.

公开(公告)号：AT127609T

公开(公告)日：1995-09-15

申请号：AT90312225

申请日：1990-11-08

Applicant: SONY CORP

Inventor： FUKAMI TADASHI ,  YAMADA MAKOTO ,  KAJIWARA TSUTOMU

IPC: G11B15/12 ,  G11B15/18 ,  G11B20/10 ,  G11B5/008

Abstract: A digital signal processing circuit being to support different arrangements of a rotary drum or the like by adapting the circuit to output a record signal at timing switched in accordance with the structure of the rotary drum and the like. The digital signal processing circuit comprises memory means for storing control data representative of the diameter of the rotary drum, the lap angle of the magnetic tape wound around the rotary drum, and the arrangement of the magnetic heads on the rotary drum; and means connected to the memory means and responsive to the stored control data for outputting the record signal at a specific transmission speed and at a timing switched as a function of the data stored in the memory means.

公开(公告)号：DE3788663T2

公开(公告)日：1994-07-21

申请号：DE3788663

申请日：1987-03-10

Applicant: SONY CORP

Inventor： FUKAMI TADASHI ,  OZAKI SHINYA ,  ODAKA KENTARO

IPC: G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30

Abstract: A rotary head type digital tape recorder in which a PCM signal and sub data for control and the like concerned with the PCM signal are recorded and/or reproduced by rotary heads. The invention relates to a method and apparatus for transmitting and/or receiving a digital signal in such a type of digital tape recorder by using a data format such that when the serial data is input and output each of a predetermined number of words of the reproduced PCM signal and each symbol of the reproduced sub data are transmitted as a pair synchronously with the rotation of the rotary heads. Thus, a large amount of sub data can be input and output together with the PCM signal.

公开(公告)号：AT99826T

公开(公告)日：1994-01-15

申请号：AT87103407

申请日：1987-03-10

Applicant: SONY CORP

Inventor： FUKAMI TADASHI ,  OZAKI SHINYA ,  ODAKA KENTARO

IPC: G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30

Abstract: A rotary head type digital tape recorder in which a PCM signal and sub data for control and the like concerned with the PCM signal are recorded and/or reproduced by rotary heads. The invention relates to a method and apparatus for transmitting and/or receiving a digital signal in such a type of digital tape recorder by using a data format such that when the serial data is input and output each of a predetermined number of words of the reproduced PCM signal and each symbol of the reproduced sub data are transmitted as a pair synchronously with the rotation of the rotary heads. Thus, a large amount of sub data can be input and output together with the PCM signal.

公开(公告)号：DE3418912C2

公开(公告)日：1993-11-18

申请号：DE3418912

申请日：1984-05-21

Applicant: SONY CORP

Inventor： FUKAMI TADASHI ,  ODAKA KENTARO

IPC: G06F7/76 ,  G11B20/12 ,  G11B20/18 ,  G11B5/09 ,  H03M13/00

Abstract: A data transmitting system uniformly processes and transmits data by taking a plurality of samples of an analog signal and generating bits forming digital words respectively corresponding to the samples, the number of bits representing each sample being switchable between a plurality of values M and N. First input data is supplied in first words of which each consists of M bits and second input data is supplied occurring in second words of which each consists of N bits. An a-th first word in each M-bit first input data is defined as Wa. The first input data is divided into k kinds of sets of (Wnk+1), (Wnk+2), . . . , (Wnk+k), where n is an arbitrary integer. A b-th word in each N-bit second input data is defined as Wb. The second input data is divided into k kinds of sets of (W'nk+1), (W'nk+2), . . . , (W'nk+k), the number of bits of the first words of the set of (Wnk+m) (m being an integer from 1 to k) being equal to the number of bits of the second words in the set of (W'nk+m). The data separately processed and transmitted in each of the sets.

公开(公告)号：AU6657390A

公开(公告)日：1991-05-30

申请号：AU6657390

申请日：1990-11-13

Applicant: SONY CORP

Inventor： FUKAMI TADASHI ,  YAMADA MAKOTO ,  KAJIWARA TSUTOMU

IPC: G11B15/18 ,  G11B20/10 ,  G11B27/032 ,  G11B27/036 ,  G11B27/10 ,  G11B27/30

Abstract: A digital signal processing circuit (8) for processing and recording data at various selectable rates, having an input/output circuit (40, 41) for receiving and outputting a digital signal; a recording circuit for generating a recording signal based on a digital signal received by the data signal processing circuit; a playback circuit (48) for retrieving recorded data; and a demodulation circuit for demodulating retrieved data. The processing and recording rates are determined by control data supplied to the circuit either via an operator or from a recorded signal.