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    1.
    发明专利
    未知

    公开(公告)号：DE69230574T2

    公开(公告)日：2000-06-21

    申请号：DE69230574

    申请日：1992-07-01

    Applicant: SONY CORP

    Inventor： HIRAMA MASAHIDE

    IPC: H01L27/146 ,  H01L27/148 ,  H04N1/028 ,  H04N1/19 ,  H04N5/335 ,  H04N5/341 ,  H04N5/357 ,  H04N5/372 ,  H04N5/376

    Abstract: The present invention intends to improve a difference between signal levels of odd-numbered pixels and even-numbered pixels in a CCD (charge coupled device) linear sensor. In a CCD linear sensor comprising a sensor region (1) having an array of a plurality of sensor elements (pixels) (S1), (S2), ... and first and second horizontal transfer registers (4) and (5) disposed on the respective sides of the sensor region (1) through read-out gate sections (2) and (3) wherein signal charges of every other sensor elements (S1), (S3), (S5), ... are transferred by the first horizontal transfer register (4) while signal charges of remaining every other sensor elements (S2), (S4), (S6) are transferred by the second horizontal transfer register (5), the first and second horizontal transfer registers (4) and (5) include first and second transfer electrodes (22R1), (22R2) to which two-phase drive pulses ( phi H1) and ( phi H2) are applied, respectively and electrode configurations at the read-out gate section side are formed substantially the same,whereby the capacity of a first transfer section (HR1) to which the drive pulse ( phi H1) is applied is made equal to that of a second transfer section (HR2) to which the drive pulse ( phi H2) is applied.

    2.
    发明专利
    未知

    公开(公告)号：DE69030788T2

    公开(公告)日：1997-09-11

    申请号：DE69030788

    申请日：1990-07-13

    Applicant: SONY CORP

    Inventor： NARABU TADAKUNI ,  HIRAMA MASAHIDE ,  NAKADA YASUO

    IPC: H04N1/028 ,  H01L27/14 ,  H04N1/03 ,  H04N1/031 ,  H04N1/19 ,  H04N1/193

    Abstract: A solid state imaging device with a plurality of line sensors (3, 4, 5, 6) in which each line sensor receives the light through the divided light paths from a straight line of a document into each unit is disclosed. The divided light paths are obtained by bending each rod lens (8) of a rod lens array (2), providing concave or convex lenses or convex mirrors or by providing transparent plates at different angles. As a result of the dividing of light path, the line sensors pick up linear image data without abutting each sensor in a straight line.

    4.
    发明专利
    未知

    公开(公告)号：DE69224255T2

    公开(公告)日：1998-08-27

    申请号：DE69224255

    申请日：1992-10-06

    Applicant: SONY CORP

    Inventor： KUNO YOSHINORI ,  HIRAMA MASAHIDE

    IPC: H01L27/148 ,  G11C19/28 ,  H01L21/339 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/762 ,  H01L29/78 ,  H01L29/772 ,  H01L29/768

    Abstract: The MOS transistor comprising channel stoppers (13a, 13b) formed of a first polysilicon layer (1 POLY) to determine a channel width (W), and a gate electrode (14) formed of a second polysilicon layer (2 POLY), wherein a bias voltage is applied to the channel stoppers (13a, 13b). In a charge detector having a source follower circuit with a drive MOS transistor and a load MOS transistor for converting a transferred signal charge into a signal voltage, the MOS transistor of the invention is used as the drive transistor, and its source output voltage is fed back as a bias voltage to the channel stoppers (13a, 13b), thereby minimizing both the DC bias variation in the output voltage of the source follower circuit and the nonuniformity in the conversion efficiency.

    6.
    发明专利
    未知

    公开(公告)号：DE69329638T2

    公开(公告)日：2001-05-03

    申请号：DE69329638

    申请日：1993-08-17

    Applicant: SONY CORP

    Inventor： HIRAMA MASAHIDE

    IPC: H04N1/028 ,  H01L27/148 ,  H04N5/335 ,  H04N5/341 ,  H04N5/347 ,  H04N5/353 ,  H04N5/372 ,  H04N5/376 ,  H04N5/378 ,  H04N3/15

    Abstract: In a CCD (charge-coupled device) device such as a one-dimensional CCD sensor or the like, a signal period during which a signal charge is read out in the intermittent mode can be extended. There is provided a CCD device in which a floating diffusion region is connected through an output gate section to the final stage of a horizontal transfer register of a CCD structure to which a transfer clock pulse is applied and in which a reset gate section is provided between the floating diffusion region and a reset drain region. When a signal charge is read out in the intermittent mode, a clock pulse ( phi OG) is applied to the output gate section to set a potential of the output gate section at low level so that a signal charge of a first pixel is accumulated in a transfer section of final stage. Then, a signal charge of a second pixel is transferred to the transfer section of the final stage by transfer clocks ( phi H1), ( phi H2), ( phi HL), whereby signal charges of two pixels are mixed within the transfer section of the final stage.

    7.
    发明专利
    未知

    公开(公告)号：DE69230574D1

    公开(公告)日：2000-02-24

    申请号：DE69230574

    申请日：1992-07-01

    Applicant: SONY CORP

    Inventor： HIRAMA MASAHIDE

    IPC: H01L27/146 ,  H01L27/148 ,  H04N1/028 ,  H04N1/19 ,  H04N5/335 ,  H04N5/341 ,  H04N5/357 ,  H04N5/372 ,  H04N5/376

    Abstract: The present invention intends to improve a difference between signal levels of odd-numbered pixels and even-numbered pixels in a CCD (charge coupled device) linear sensor. In a CCD linear sensor comprising a sensor region (1) having an array of a plurality of sensor elements (pixels) (S1), (S2), ... and first and second horizontal transfer registers (4) and (5) disposed on the respective sides of the sensor region (1) through read-out gate sections (2) and (3) wherein signal charges of every other sensor elements (S1), (S3), (S5), ... are transferred by the first horizontal transfer register (4) while signal charges of remaining every other sensor elements (S2), (S4), (S6) are transferred by the second horizontal transfer register (5), the first and second horizontal transfer registers (4) and (5) include first and second transfer electrodes (22R1), (22R2) to which two-phase drive pulses ( phi H1) and ( phi H2) are applied, respectively and electrode configurations at the read-out gate section side are formed substantially the same,whereby the capacity of a first transfer section (HR1) to which the drive pulse ( phi H1) is applied is made equal to that of a second transfer section (HR2) to which the drive pulse ( phi H2) is applied.

    8.
    发明专利
    未知

    公开(公告)号：DE69228838T2

    公开(公告)日：1999-10-21

    申请号：DE69228838

    申请日：1992-07-09

    Applicant: SONY CORP

    Inventor： HIRAMA MASAHIDE

    IPC: G11C27/04 ,  H01L27/148 ,  H04N5/335 ,  H04N5/341 ,  H04N5/372 ,  H04N3/15

    Abstract: The present invention relates to a method of driving a charge transfer device comprising: a charge detecting section including an electrically floating diffusion region (7; 27), a output amplifier (8; 28) connected to said floating diffusion region (7; 27) and a transistor responsive to a reset pulse voltage signal ( phi RG) for resetting said floating diffusion region (7; 27) to a predetermined potential. The transistor comprises said floating diffusion region (7; 27), a reset drain region (10; 30) formed in a substrate (2), a gate electrode (11; 29) connected to a source of said reset pulse voltage signal ( phi RG), and a channel formed on said substrate (2), said channel extending between said floating diffusion region (7; 27) and said reset drain region (10; 30). Charge transfer means transfer charges to said charge detecting section, and include a channel formed on said substrate, a plurality of gate electrodes insulated from said channel, and an output gate electrode formed on an end of said charge transfer means. In this method an output gate pulse voltage signal (VHOG) having an anti-phase of said reset pulse voltage signal ( phi RG) is to be applied to said output gate electrode.

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