公开(公告)号：WO0018127A9

公开(公告)日：2000-06-29

申请号：PCT/JP9905168

申请日：1999-09-21

Applicant: SONY CORP ,  KONDO TETSUJIRO ,  HORISHI TAKASHI

Inventor： KONDO TETSUJIRO ,  HORISHI TAKASHI

IPC: H04N19/14 ,  G06T9/00 ,  H04N19/119 ,  H04N19/149 ,  H04N19/176 ,  H04N19/423 ,  H04N19/46 ,  H04N19/60 ,  H04N19/70 ,  H04N19/85 ,  H04N19/98 ,  H04N7/26

CPC classification number: H04N19/98 ,  H04N19/124 ,  H04N19/14 ,  H04N19/149 ,  H04N19/176 ,  H04N19/182 ,  H04N19/42 ,  H04N19/60 ,  H04N19/70

Abstract: Since the edge portion is disadvantageous in terms of the amount of information in normal coding, conventionally the distortion due to quantization increases when normal coding is performed. A coding device of the invention comprises a blocking section which divides image data into blocks, an amount-of-data calculating section which calculates the amount of information on the coding of the blocked image data, a pixel exchanging section which exchanges pixels between a block for which the amount of information is calculated by the amount-of-information calculating section and an arbitrary block, a controller which compares the amount of information of the block for which a pixel is exchanged by the pixel exchanging section with the amount of information of the block before the pixel exchange and determines a block to be sent to a quantizing section according to the results of the comparison, the quantizing section which subjects the block sent from the pixel exchanging section to ADRC quantization, and a multiplexing section which adds additional information to ADRC-quantized data from the quantizing section.

Abstract translation: 由于边缘部分在正常编码中的信息量方面是不利的，所以通常在执行正常编码时由于量化引起的失真增加。 本发明的编码装置包括将图像数据分割成块的阻挡部分，数据量计算部分，其计算关于阻挡图像数据的编码的信息量;像素交换部分，其在块 由信息量计算部和任意块计算信息量的控制器，将由像素交换部交换的像素的块的信息量与 在像素交换之前的块，并且根据比较结果确定要发送到量化部分的块，将从像素交换部发送的块进行ADRC量化的量化部分，以及添加附加信息的复用部分 来自量化部分的ADRC量化数据。

公开(公告)号：DE69736257D1

公开(公告)日：2006-08-10

申请号：DE69736257

申请日：1997-05-30

Applicant: SONY CORP

Inventor： HORISHI TAKASHI ,  UCHIDA MASASHI ,  KONDO TETSUJIRO

IPC: H04N7/01 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50

Abstract: An ADRC circuit 3 generates spatial classes with SD data extracted by an area extracting circuit 2. A moving class determining circuit 5 generates a moving class with SD data extracted by an area extracting circuit 4. A class code generating circuit 6 generates a class code with the spatial class and the moving class. A tap decreasing ROM 7 supplies additional code data for each class code to a tap decreasing code 10. The additional code data is used to decrease taps of SD data. The tap decreasing circuit 10 decreases the SD data extracted by an area extracting circuit 9. A prediction calculating circuit 11 receives coefficient data corresponding to the class code from a ROM table 8 and obtains HD data with the decreased SD data corresponding to a linear prediction equation.

公开(公告)号：EP0664525A4

公开(公告)日：1995-12-06

申请号：EP94921830

申请日：1994-07-28

Applicant: SONY CORP

Inventor： KONDO TETSUJIRO ,  HORISHI TAKASHI

IPC: G06T7/00 ,  G06T7/20

CPC classification number: G06T7/238

公开(公告)号：EP0843475A4

公开(公告)日：2000-04-12

申请号：EP97924276

申请日：1997-05-30

Applicant: SONY CORP

Inventor： HORISHI TAKASHI ,  UCHIDA MASASHI ,  KONDO TETSUJIRO

IPC: H04N7/01 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50

CPC classification number: H04N7/0135 ,  H04N7/01 ,  H04N7/0125 ,  H04N7/0145 ,  H04N19/117 ,  H04N19/136 ,  H04N19/172 ,  H04N19/587 ,  H04N19/59 ,  H04N19/61 ,  H04N19/98

Abstract: An ADRC circuit (3) generates a space class from SD data segmented by an area segmenting circuit (2) and a motion class deciding circuit (5) generates a motion class from the SD data segmented by an area segmenting circuit (4). A class code generating circuit (6) generates a class code from the space class and motion class. The additional code data which degenerate the tap of the SD data at every class code are supplied to a tap degenerating circuit (10) from a tap degeneration ROM (7) and the circuit (10) degenerates the SD data segmented by an area segmenting circuit (9). An estimating arithmetic circuit (11) obtains HD data by estimating the linearity between the coefficient data corresponding to the class codes and supplied from a ROM table (8) and the degenerated SD data.

公开(公告)号：EP1734478A4

公开(公告)日：2011-04-13

申请号：EP05728519

申请日：2005-04-08

Applicant: SONY CORP

Inventor： HORISHI TAKASHI ,  YOSHIWARA NORIFUMI ,  NAKAMURA YUKIHIRO ,  KAINO AKIHIKO ,  KAWAGUCHI KUNIO ,  TAKAHASHI YASUAKI ,  CHOKI YUTA ,  KONDO TETSUJIRO

IPC: G06T7/20 ,  G06T3/40 ,  H04N5/14 ,  H04N7/01 ,  H04N7/12

CPC classification number: H04N5/145 ,  G06T3/4007 ,  G06T7/254 ,  H04N7/014

公开(公告)号：DE69942086D1

公开(公告)日：2010-04-15

申请号：DE69942086

申请日：1999-09-21

Applicant: SONY CORP

Inventor： KONDO TETSUJIRO ,  HORISHI TAKASHI

IPC: H04N19/14 ,  H04N1/41 ,  H04N11/04 ,  H04N19/00 ,  H04N19/102 ,  H04N19/103 ,  H04N19/136 ,  H04N19/176 ,  H04N19/186 ,  H04N19/196 ,  H04N19/423 ,  H04N19/46 ,  H04N19/593 ,  H04N19/70 ,  H04N19/91

Abstract: Hitherto, in order to encode digital image signals, a rather large amount of data is applied to an edge part. There is inevitably a limit to the reduction of data, and the efficiency of encoding the image signals is low. In the encoding apparatus, the image signals provided in units of frames, each having a plurality of pixel data items, are divided into macro groups, and the pixel data items in each macro group are combined, forming a group. The pixel data items of the group are encoded on the basis of the level data representing the signal level of the representative pixel data item in the group, the position data concerning all pixel data items of the group and the data representing the number of the pixel data items existing in the group.

公开(公告)号：AU719477B2

公开(公告)日：2000-05-11

申请号：AU5410398

申请日：1997-12-11

Applicant: SONY CORP

Inventor： HORISHI TAKASHI ,  KONDO TETSUJIRO

IPC: H04N5/14 ,  H04N5/44 ,  H04N7/01 ,  H04N9/64 ,  H04N11/20

Abstract: An SD pixel of a luminance signal is held by a delay register section (31), and the class of the SD pixel is discriminated by a classifying section (33). A coefficient corresponding to the result of discrimination is read out of a coefficient RAM section (40) and outputted to a product-sum section (38). Pixel data of 17 taps are taken from the delay register section (31), then converted to 7 taps, and thus outputted to the product-sum section (38). The product-sum section (38) carries out product-sum operation of the pixel data and the coefficient, and outputs the result of operation as an HD pixel. An interpolation pixel operating section (42) carries out simple interpolation of pixel data of a color-signal component which is different from interpolation in the case of a luminance signal, and generates an HD pixel of the color signal. Thus, miniaturization and reduction in cost are realized.

公开(公告)号：MX9805333A

公开(公告)日：1998-10-31

申请号：MX9805333

申请日：1998-06-30

Applicant: SONY CORP

Inventor： HORISHI TAKASHI ,  KONDO TETSUJIRO

IPC: H04N5/14 ,  H04N5/44 ,  H04N7/01 ,  H04N9/64 ,  H04N07/01

Abstract: Una seccion 31 de registro de retardo retiene los pixeles SD de una señal de luminancia y una seccion 33 de clasificacion decide una clase, lee un coeficiente que corresponde al resultado de la decision de una seccion 40 de RAM coeficiente y envía el coeficiente a una seccion 38 de suma de producto. La seccion 38 de suma de producto captura el dato de pixel 17 derivaciones desde la seccion 31 de registro de retardo, convierte el dato de pixel en 7 derivaciones y envía las mismas a la seccion 38de suma del producto. La seccion 38 de suma del producto lleva a cabo la operacion de suma del producto de los datos de pixel y los coeficiente y envía el resultado de la operacion como pixeles HD. Una seccion 42 de operacion de pixel de interpolacion aplica un procesamiento de interpolacion sencillo diferente el caso de una señal de luminancia al dato de pixel de un componente de la señal a colores para generar pixeles HD de una señal a colores. De esta manera, se puede obtener un tamaño menor y reduccion en costo.

公开(公告)号：DE69731872D1

公开(公告)日：2005-01-13

申请号：DE69731872

申请日：1997-05-30

Applicant: SONY CORP

Inventor： HORISHI TAKASHI ,  UCHIDA MASASHI ,  KONDO TETSUJIRO

IPC: H04N7/01 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50

Abstract: An ADRC circuit 3 generates spatial classes with SD data extracted by an area extracting circuit 2. A moving class determining circuit 5 generates a moving class with SD data extracted by an area extracting circuit 4. A class code generating circuit 6 generates a class code with the spatial class and the moving class. A tap decreasing ROM 7 supplies additional code data for each class code to a tap decreasing code 10. The additional code data is used to decrease taps of SD data. The tap decreasing circuit 10 decreases the SD data extracted by an area extracting circuit 9. A prediction calculating circuit 11 receives coefficient data corresponding to the class code from a ROM table 8 and obtains HD data with the decreased SD data corresponding to a linear prediction equation.

公开(公告)号：DE69722381D1

公开(公告)日：2003-07-03

申请号：DE69722381

申请日：1997-12-11

Applicant: SONY CORP

Inventor： HORISHI TAKASHI ,  KONDO TETSUJIRO

IPC: H04N5/14 ,  H04N5/44 ,  H04N7/01 ,  H04N9/64 ,  H04N11/20

Abstract: An SD pixel of a luminance signal is held by a delay register section (31), and the class of the SD pixel is discriminated by a classifying section (33). A coefficient corresponding to the result of discrimination is read out of a coefficient RAM section (40) and outputted to a product-sum section (38). Pixel data of 17 taps are taken from the delay register section (31), then converted to 7 taps, and thus outputted to the product-sum section (38). The product-sum section (38) carries out product-sum operation of the pixel data and the coefficient, and outputs the result of operation as an HD pixel. An interpolation pixel operating section (42) carries out simple interpolation of pixel data of a color-signal component which is different from interpolation in the case of a luminance signal, and generates an HD pixel of the color signal. Thus, miniaturization and reduction in cost are realized.