公开(公告)号：JPH0962484A

公开(公告)日：1997-03-07

申请号：JP24098195

申请日：1995-08-25

Applicant: SONY CORP

Inventor： KAI MASAMITSU

IPC: G06F5/06 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To effectively use the capacity of a buffer memory by making it possible to transfer data from the address of an arbitrary border of the buffer memory, for example, when four 8-bit DRAMs are used to enable 32-bit data transfer to the buffer memory. SOLUTION: The buffer memory 19 is constituted by using, for example, four 8-bit DRAMs 50-52 so that 32-bit data transfer can be performed. To transfer data from the addresses of borders of the DRAMs 50-52 to the buffer memory, dummy data are added up to the borders and writing to the DRAMs at the places to which the dummy data are transferred is made ineffective with signals CASO-CAS3. To transfer data from the addresses of the borders of the DRAMs from the buffer memory, the data up to the places of the borders are removed and the data are transferred.

公开(公告)号：JPH01309476A

公开(公告)日：1989-12-13

申请号：JP14027088

申请日：1988-06-07

Applicant: SONY CORP

Inventor： TAKAYAMA YOSHIHISA ,  KAI MASAMITSU ,  NAKAMURA TOSHINORI ,  KUSAKABE SUSUMU

IPC: H04N5/278 ,  G06T1/60

Abstract: PURPOSE:To improve the processing speed and to reduce the cost by providing an exclusive arithmetic unit so as to control an address of a source memory and an output memory and using a DMA(direct memory access) so as to write a picture data subject to arithmetic processing to the output memory at a high speed. CONSTITUTION:A picture data in data such as picture data and processing data supplied from a data storage section 10 to an arithmetic section 30 is written in a source RAM 33 and the processing data is written in a RAM of a microcomputer 31. When the calculation of the picture data is needed, the readout address of the source RAM 33 and the write address of the output RAM 34 in the exclusive arithmetic unit 32 are controlled. Then the picture data written in the prescribed address of the source RAM 33 is written in the prescribed address of the output RAM 34. That is, the picture data subject to arithmetic processing is written in the output RAM 34 at a high speed.

公开(公告)号：JPH01309477A

公开(公告)日：1989-12-13

申请号：JP14027188

申请日：1988-06-07

Applicant: SONY CORP

Inventor： TAKAYAMA YOSHIHISA ,  KAI MASAMITSU ,  NAKAMURA TOSHINORI ,  KUSAKABE SUSUMU

IPC: H04N5/278

Abstract: PURPOSE:To send plural telops smoothly by sending the telop in the order of transmission every time a telop transmission key is depressed and displaying the telop to be sent next onto a display device for pre-view. CONSTITUTION:When a telop transmission key of an input device 23 is depressed, a picture data of the telop of a transmission number 1 and the corresponding processing data are read from a disk 13 and fed to an arithmetic section 30. Thus, the picture data for the telop is fed to a video device 35 from an output RAM 34 and the telop of the transmission number 1 is displayed on a monitor receiver 41. Every time the telop transmission key of the input device 23 is depressed, the similar operation is repeated and the telop is sent and the succeeding telop is displayed on the monitor receiver 21. Thus, plural telops are sent smoothly and the telop sent next is ensured and mistransmission is prevented.