公开(公告)号：DE602006015141D1

公开(公告)日：2010-08-12

申请号：DE602006015141

申请日：2006-11-08

Applicant: SONY CORP

Inventor： KURE YOSHINOBU ,  KAWADA MASATO

IPC: H04L1/18 ,  H04L1/00 ,  H04L29/08

公开(公告)号：EP2175628A4

公开(公告)日：2011-05-04

申请号：EP08778360

申请日：2008-07-24

Applicant: SONY CORP

Inventor： KAWADA MASATO ,  ASAUMI YOSHIYA ,  MASUDA YASUTO

IPC: H04M3/42 ,  H04L29/06 ,  H04L29/08 ,  H04M7/12

CPC classification number: H04M3/42008 ,  H04M3/42059 ,  H04M3/42093 ,  H04M7/006 ,  H04M7/127 ,  H04M2242/22

公开(公告)号：JPH0685585A

公开(公告)日：1994-03-25

申请号：JP25552892

申请日：1992-08-31

Applicant: SONY CORP

Inventor： KAWADA MASATO ,  FURUYA YOSHINAGA ,  KAWAI RIYUUICHIROU

IPC: H03G11/00 ,  H03F1/42 ,  H03G3/10

Abstract: PURPOSE:To provide the gain control amplifier circuit which is operated over a much wider band than the conventional circuit and improves a signal noise ratio (S/N). CONSTITUTION:Concerning the gain control amplifier circuit which defines a Gilbert amplifier circuit as the basic configuration and is composed of a preceding step gain control amplifier circuit provided with a directly proportional amplifying characteristic and a following step gain control amplifier circuit provided with an inversely proportional amplifying characteristic, the load resistor of a second differential amplifying step 11B constituting an output step 12 in the preceding step is multicoupled with the logarithm amplifying means of a gain control means 12A constituting an input step 11 in the following step. Thus, the circuit configuration of a gain control amplifier circuit 10 is simplified, an arbitrary gain can be provided by adjusting a current ratio between first and second current sources 5 and 13, and energy consumption or the S/N can be more improved in comparison with the conventional circuit.

公开(公告)号：JPH0722844A

公开(公告)日：1995-01-24

申请号：JP18927493

申请日：1993-06-30

Applicant: SONY CORP

Inventor： KAWADA MASATO ,  FURUYA YOSHINAGA ,  KAWAI RIYUUICHIROU

IPC: G01R19/04 ,  H03D1/10

Abstract: PURPOSE:To reduce the number of terminals by selecting the analog signal processing characteristic obtained by an amplifying means and a capacitor and the characteristic, where this analog signal processing characteristic and another analog signal processing characteristic obtained by another amplifying means and capacitor are added, by the control of a switch means. CONSTITUTION:The peak hold characteristic obtained by a peak hold 23 and a hold capacitor 25 and the characteristic where this peak hold characteristic and another peak hold characteristic obtained by a peak hold 27 and a hold capacitor 29 are added are selected by the control of a switch 26. The number of terminals 24 and 28 for hold capacitor is reduced from three to two to use the circuit in an integrated circuit lacking for terminals. An on/off switch simpler than a conventional two-input and one-output switch is used as the switch 26. The peak hold 23 and the hold capacitor 25 are shared between the single peak hold mode and the double peak hold mode to reduce the number of circuits and hold capacitors.

公开(公告)号：JPH02128524A

公开(公告)日：1990-05-16

申请号：JP28144788

申请日：1988-11-09

Applicant: SONY CORP

Inventor： KOMATSU SADAHIRO ,  YOSHII YOJI ,  KAWADA MASATO

IPC: H03M1/14 ,  H03M1/36

Abstract: PURPOSE:To correct a higher-order conversion code and to easily constitute an AD converting circuit at the time of making the circuit into an IC by extending the width of a lower-order digitized conversion level. CONSTITUTION:In a serial-parallel type AD converting circuit which converts an analog signal to a digital signal in two stages, switching blocks are arranged in a matrix, and folding points of reference resistance lines are successively shifted by a half cycle to supply reference voltages, which are applied to respective switching blocks, from connection points of respective reference resistances. Switching blocks connected to the same reference voltage are integrated to not only simplify the matrix circuit but also reduce the number of lower-order comparators. Thus, a reference voltage applying circuit length is equally set for respective switching blocks, and the number of switching blocks is reduced, and the circuit scale is more simplified according as the number of conversion bits is increased.

公开(公告)号：JPH0654228A

公开(公告)日：1994-02-25

申请号：JP22530792

申请日：1992-07-31

Applicant: SONY CORP

Inventor： KAWAI RIYUUICHIROU ,  FURUYA YOSHINAGA ,  KAWADA MASATO

IPC: H03G11/00 ,  H04N5/18

Abstract: PURPOSE:To secure the small and stable value of the difference voltage by adjusting the value of the mutual conductance with the adjustment signal acquired from the outside. CONSTITUTION:A video signal clamping circuit 6 calmps the DC component of an input analog signal S1 at a prescribed level and outputs it as an output analog signal S2. At the same time, the circuit 6 detects the difference level by a voltage/current converter circuit 7 to the reference DC level Vref of the signal S2 and outputs the charging/discharging current (i) based on the difference voltage to apply the feedback control to the current (i) of a capacitor 5 which sets a clamp level. Then, the converter 7 converts the difference voltage into the current (i) proportional to the mutual conductance value set based on a mutual conductance adjustment signal S4 and outputs the current (i). In such a constitution, the circuit 6 can easily control the mutual inductance value to an optimum level and also can reduce the difference voltage.

公开(公告)号：JPH0226130A

公开(公告)日：1990-01-29

申请号：JP17506088

申请日：1988-07-15

Applicant: SONY CORP

Inventor： NOJIMA KAZUHISA ,  KOMATSU SADAHIRO ,  YANO MOTOYASU ,  KAWADA MASATO

IPC: H03M7/00

Abstract: PURPOSE:To obtain a high operating speed and low energy consumption by using a Multi Level Emitter Coupled Logic(MEL) circuit. CONSTITUTION:For example, input signals D4i-d7i of the binary code of four bits D4-D7 are defined as first and second logic level signals and a specified logical product signal in level shift circuits 1 and 2 and supplied to a decoder circuit 3 which uses the MEL circuit. A 2 -number of codes, in which the number of 1 level is continued, are formed in correspondence to the MEL unit circuit and (n)-bit code of the circuit 3. After that, a thermometer code to be converted to codes E1-E15 is outputted. Since these level shifter and EML circuit are used and the simple constitution, in which a NAND gate is not laminated, is obtained, the high operating speed and low energy consumption can be obtained.

公开(公告)号：JPH0722877A

公开(公告)日：1995-01-24

申请号：JP18900493

申请日：1993-06-30

Applicant: SONY CORP

Inventor： KAWADA MASATO ,  FURUYA YOSHINAGA ,  KAWAI RIYUUICHIROU

IPC: H03G3/00

Abstract: PURPOSE:To reduce the number of circuit parts.by detecting the input signal applied to a first or second input terminal by a detecting circuit and switching the switch of a switching circuit based on the detection result. CONSTITUTION:When the bias voltage level of an adjustment signal S2 is higher than a reference level, an adjustment signal detecting circuit 13 switches the switch of a switch circuit 11 to the side of an input terminal 11A by a switching signal SW to give the adjustment signal S2 to an amplifying circuit 12. When the bias voltage level of the adjustment signal S2 is lower than the reference level, the switch of the switch circuit 11 is switched to the side of an input terminal 11B by the switching signal SW to give a main signal S1 to the amplifying circuit 12. At the time of adjustment of the gain of the amplifying circuit, the adjustment signal S2 is given to an input terminal P12, and a monitor is so observed that an output signal SOUT of an output terminal P13 becomes a prescribed level, and a gain adjustment signal S3 given to a terminal P14 for gain adjustment is controlled.

公开(公告)号：JPH0654226A

公开(公告)日：1994-02-25

申请号：JP22497192

申请日：1992-07-31

Applicant: SONY CORP

Inventor： KAWADA MASATO ,  FURUYA YOSHINAGA ,  KAWAI RIYUUICHIROU

IPC: H04N5/14 ,  H04N5/16

Abstract: PURPOSE:To amplify the signal level to an optional level and to output the signal with no deterioration of the SN ratio by amplifying the sampled signal level with combination of an amplifying means having a fixed smplification factor and an attenuating means which can vary its attenuation factor. CONSTITUTION:A CCD signal processing circuit 10 samples a color signal level of the CCD output signal S1 of a CCD element 2 by a sample and hold circuit 4 and supplies the sampled signal level to an amplifier 11. The gain of an amplified signal S2 is controlled based on a voltage source E1 and with variation of the dividing ratio of a variable resistance R1. Then, the voltage that internally divided the source E1 and the signal S2 is outputted to an amplifier 6 as the attenuated voltage. Meanwhile, the output of the fixed amplifier 11 and a potential equal to the source E1 during the operation of a clamping circuit 7. Thus no potential difference is produced between the output terminal of the amplifier 11 and the source E1. Therefore, the voltage inputted to the amplifier 6 in a clamping period is always set at a fixed black level regardless of the resistance value of the resistance R1.

公开(公告)号：JPH04185112A

公开(公告)日：1992-07-02

申请号：JP31641590

申请日：1990-11-20

Applicant: SONY CORP

Inventor： KOMATSU SADAHIRO ,  KAWADA MASATO

IPC: H03M1/36 ,  H03K3/2885 ,  H03K19/086 ,  H03K19/20

Abstract: PURPOSE:To make the entire circuit constitution small by connecting plural output transistors(TRs) in cascode to the output electrode of one TR being a component of a differential circuit to shunt a current flowing to the one TR by the number of output TRs. CONSTITUTION:With an inverting clock signal inverse of CLK at an H level, TRs Q27, Q37, Q61 are turned on in the collector dot AND circuit, and a reference signal and the input analog signal are compared by 1st-3rd differential circuits 1-3. Thus, a current flows to collectors of TRs being components of each of the 1st-3rd differential circuits 1-3. In this case, the output current of each TR being a component of the 1st-3rd differential circuits 1-3 is shunted two systems by providing TRs Q26, Q29, Q32, Q34, Q60, Q63, Q66, Q68 in cascode connection. Thus, the circuit is formed without addition of a gate. Thus, the entire circuit constitution is made small.