公开(公告)号：JP2002222956A

公开(公告)日：2002-08-09

申请号：JP2001016885

申请日：2001-01-25

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/308 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device improved so that a parasitic MOSFET may not be formed even when a Mesa type isolation technique or an STI isolating method is applied to form a MOSFET in an SOI layer. SOLUTION: The method for manufacturing the semiconductor device comprises the step of removing a semiconductor layer (SOI layer) from an element isolation region by etching in an element isolating step of isolating to form a plurality of element regions. The method further comprises the step of forming a thermal oxide film on a sidewall of the SOI layer 3 in a step of forming an insulating layer. The method also comprises the steps of then removing an element isolating mask, and then forming a sidewall 8 of an Si3N4 on a sidewall face of the SOI layer 3. The method also comprises the steps of thereafter etching the SOI layer 3 with an ammonia hydrogen peroxide water in the etching step, and finally forming an oxide film 9 an electrode 10 to complete the MOSFET.

公开(公告)号：JP2001244269A

公开(公告)日：2001-09-07

申请号：JP2001027767

申请日：2001-02-05

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a wiring formation method which prevents the crystal particle of an Al film formed on a barrier metal film from becoming fine and which solves the problem of a drop in electromigration-resistance. SOLUTION: The wiring formation method comprises a process in which a barrier layer 6 is formed on the whole face of a substrate 1 including a step recessed part so as to be thin and in a conformal manner. The method comprises a process in which a diffusion preventive layer 8 is formed thin in parts other than at least the bottom of the step recessed part. The method comprises a process in which an aluminum-based wiring material 4 is formed on the whole face of the substrate.

公开(公告)号：JP2001053281A

公开(公告)日：2001-02-23

申请号：JP22735099

申请日：1999-08-11

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L29/786 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To provide a full depleted SOI semiconductor device provided with a back gate electrode, where a semiconductor layer (SOI layer) just under a gate electrode is small in thickness, and other semiconductor layers other than the SOI layer are large in thickness and low in resistance. SOLUTION: An SOI semiconductor device consists of an interlayer film 18 formed on a support substrate 20, an insulating layer 14 formed on the interlayer film 18, a semiconductor layer 10A formed on the surface of the insulating layer 14 and surrounded with the insulating layer 14, source/drain regions 34 and a channel forming region 35 formed in the semiconductor layer 10A, a gate electrode 31 formed on the channel forming region 35 through the intermediary of a gate insulating film 30, a groove 15 extended inside the semiconductor layer 10A penetrating through the insulating layer 14, a back gate electrode 17 which is formed of conductive material and filled in the groove 15, and an oxide film 16 formed between the back gate electrode 17 and the semiconductor layer 10A.

公开(公告)号：JPH11163127A

公开(公告)日：1999-06-18

申请号：JP32264297

申请日：1997-11-25

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To obtain a multilayered wiring, having a bordrless connection holes, and the method of manufacturing the multilayered wiring. SOLUTION: A first insulating layer 13 is formed on a substrate 11, and a groove wiring 21 is formed on the first insulating layer 13. The second insulating layer 31, covering the groove wiring 21, is formed on the first insulating layer 13, and a connection hole 32, communicating with the groove wiring 21, is provided on the second insulating layer 31. At the time, at least the upper layer of the first insulating layer 13 consists of an etching suppressing layer 14 which is hardly etched more than the second insulating layer 31, and the bottom part 32B of the connection hole 32 is formed above the groove wiring 21 in the etching suppressing layer 14.

公开(公告)号：JPH1154621A

公开(公告)日：1999-02-26

申请号：JP21337097

申请日：1997-08-07

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can effectively suppress the deterioration of wiring reliability due to electronic migration and an inter- wiring shorting failure, while the increase of inter-wiring capacitance is avoided even if a low dielectric film is applied to a groove wiring technology, and to provide a manufacturing method. SOLUTION: An upper-layer wiring groove is formed on an interlayer insulating film 9, and at least a part of a side wall film 12 is left to hight higher than the base of the upper-layer wiring groove at that time. Then, a TiN/Ti film 14 is formed on the entire face, and an Al alloy film is formed on it. The Al alloy film is reflowed with a high pressure and is embedded into a connection hole 11 and the upper-layer wiring groove. Then, the connection hole 11, the Al alloy film at a part, except for the inner part of the upper layer wiring groove and the TiN/Ti film 14, are removed by a CMP method and an upper- layer groove wiring 15 is formed.

公开(公告)号：JPH10270548A

公开(公告)日：1998-10-09

申请号：JP6823097

申请日：1997-03-21

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To impart high reliability for suppressing the deterioration of EM (electromigration) resistance and the increase in contact resistance by preventing the reduction of the contact area between an upper wiring layer and a connecting plug in a connecting hole for connection with the wiring layer for the borderless connecting-hole wiring structure of a semiconductor device having a borderless connecting-hole wiring structure. SOLUTION: This manufacturing method has (a) the process for forming a connecting hole 3 in an innerlayer insulating film 2 on a substrate 1, (b) the process for forming a connecting plug 4 by embedding conducting material in the connecting hole 3 and (c) the process for forming an upper wiring layer 5 on the innerlayer insulating film 2. In this case, the connecting plug is formed so that the connecting-plug length becomes shorter than the depth of the connecting hole in the process (b). In the process (c), even when the upper wiring layer does not cover the entire surface of the opening surface of the connecting hole, a part of the upper wiring layer is embedded in the connecting hole so that the upper surface of the connecting plug or the upper surface of a contact layer for the upper wiring layer formed at the part thereof is not exposed.

公开(公告)号：JPH10242271A

公开(公告)日：1998-09-11

申请号：JP6184697

申请日：1997-02-28

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can especially cope with borderless groove wiring structure, having structure capable of suppressing the decrease of the contact area between wiring material and connection hole filling material and reducing the rise of contact resistance, even if the deviation of alignment of an upper-layer wiring groove occurs to the connection hole, and the wiring groove goes partially wide of the connection hole, and its manufacture. SOLUTION: In a semiconductor device which has such a structure that a connection plug 5 is made by filling a connection hole 3 made in the interlayer insulating film 2 on a substrate 1 with connection hole filling material, that a wiring groove 6 is made in the interlayer insulating film 2 after formation of the connection plug 5, and that groove winding 8 is made by filling the wiring groove 6 with wiring material, the connection plug 5 is made to penetrate the groove wiring 8 so that at least one part of the flank of the connection plug 5 may come into contact with the groove wiring 8.

公开(公告)号：JPH1064908A

公开(公告)日：1998-03-06

申请号：JP23131796

申请日：1996-08-13

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L21/285 ,  C23C14/02 ,  H01L21/203 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a wiring of a semiconductor device in which crystal orientation property of a wiring material layer formed on an insulating layer is improved by preventing a Si rich layer, which is formed when sputter-etch-cleaning process is applied on the surface of the insulating layer, from re-oxidizing. SOLUTION: A method for forming a wiring of a semiconductor device comprises a process for forming an insulating layer of silicon system material on a base body, a process for applying spatter-etch-cleaning process to the surface of the insulating layer, a process for forming a wiring material layer on the insulating layer in sputtering manner, and a process for patterning the wiring material layer on the insulating layer to form a wiring. In the process for sputter-etch-cleaning process, the process is performed while cooling the base body.

公开(公告)号：JPH0964173A

公开(公告)日：1997-03-07

申请号：JP20983395

申请日：1995-08-18

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To reduce friction between a wiring formation layer and a substrate and hence bury the wiring formation layer in the interior of a connection hole by forming a substrate lubricating layer comprising a metal material having a lower melting point than a reflow temperature of the wiring formation layer on a side wall upper part of the connection hole and on a substrate layer around the side wall upper part to melt the substrate lubricating layer upon reflowing. SOLUTION: A substrate layer 12 is formed on a substrate 11, and a connection hole 13 is formed in the substrate layer 12. There is formed a substrate lubricating layer 14 is formed on an upper side part of the connection hole 13 and on the substrate layer 12, the substrate lubricating layer 14 comprising a metal material having a lower melting point than a reflow temperature of a wiring formation layer 15. Thereafter, the wiring formation layer 15 is formed on the substrate layer 12 so as to cover the upper portion of the connection hole 13. Hereby, the substrate lubricating layer 14 is melted upon reflowing so that there is reduced friction between the wiring formation layer 15 and the substrate layer 12. For this, the wiring formation layer 15 is facilitated to enter the connection hole 13. Thus, the wiring formation layer 15 can be buried in the connection hole very easily and satisfactorily.

公开(公告)号：JPH08186175A

公开(公告)日：1996-07-16

申请号：JP33920794

申请日：1994-12-28

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768

Abstract: PURPOSE: To provide a wiring-formed method of a semiconductor, in which a short circuit, breaking or an increase of resistance of wiring by separation of impurity particles in a metal wiring material layer formed by a PVD method is. CONSTITUTION: A gate oxide film of SiO2 is formed on a surface of substrate after forming an element separating region 11 of LOCOS structure on a Si substrate 10. After forming a polyside gate electrode 13, an ion is injected for forming LDD structure, an SiO2 film is deposited on all surface and etch backed and, a gate side wall is formed. After an impurity ion is injected, a source.drain region 15 is formed by activating heat treatment. An SiO2 insulation layer 20 is formed by a CVD method on the substrate, an opening 21 is formed, a Ti layer for decreasing contact resistance, and a barrier layer TiN layer are formed by sputtering on the insulation layer as an under layer 22. After forming wiring material layer 23 of Al-0.5%Cu by the sputtering, the wiring layer is reflow-treated in an inert gas an connecting holes 24 are formed. As it is quenched after the reflow treatment coarse particles of Cu are not separated, and reliable wiring layers 25 is obtained after aging.