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公开(公告)号：DE60200579D1
公开(公告)日：2004-07-08
申请号：DE60200579
申请日：2002-02-20
Applicant: SONY CORP
Inventor： NAKAJIMA KEN , MITSUI SATOSHI
Abstract: The present invention relates to an image noise reduction method and apparatus to be preferably used to digitize and process, for example, an image signal. Therefore, in the case of the present invention, level values a to h of peripheral pixels and the level value o of a watched pixel are respectively input to, for example, eight comparators 11 and the value "1" is output when absolute values of differences between the level values are smaller than the value of a reference level &thetas;. Moreover, peripheral pixels at point-symmetric positions about the watched pixel o are combined and signals output from the comparators 11 are supplied to four AND circuits 12 in accordance with combinations. Then, signals output from the AND circuits 12 are supplied to eight AND gates 13 in accordance with each combination and level values a to h of corresponding peripheral pixels are output to output ports 3 through the AND gates 13 when signals output from the AND circuits 12 respectively have the value "1". Moreover, signals output from the AND circuits 12 are supplied to an adder 14, the addition output is doubled by a multiplier 15, and the value "1" is added to the multiplication value and output to an output port 4. Thereby, it is possible to perform the averaging operation by using only pixels in which pixels at point-symmetric positions about, for example, a watched pixel are combined and both are selected and thereby, it is possible to solve the problem that an averaged signal phase is deviated from an original position.
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公开(公告)号：DE60200579T2
公开(公告)日：2005-06-16
申请号：DE60200579
申请日：2002-02-20
Applicant: SONY CORP
Inventor： NAKAJIMA KEN , MITSUI SATOSHI
Abstract: The present invention relates to an image noise reduction method and apparatus to be preferably used to digitize and process, for example, an image signal. Therefore, in the case of the present invention, level values a to h of peripheral pixels and the level value o of a watched pixel are respectively input to, for example, eight comparators 11 and the value "1" is output when absolute values of differences between the level values are smaller than the value of a reference level &thetas;. Moreover, peripheral pixels at point-symmetric positions about the watched pixel o are combined and signals output from the comparators 11 are supplied to four AND circuits 12 in accordance with combinations. Then, signals output from the AND circuits 12 are supplied to eight AND gates 13 in accordance with each combination and level values a to h of corresponding peripheral pixels are output to output ports 3 through the AND gates 13 when signals output from the AND circuits 12 respectively have the value "1". Moreover, signals output from the AND circuits 12 are supplied to an adder 14, the addition output is doubled by a multiplier 15, and the value "1" is added to the multiplication value and output to an output port 4. Thereby, it is possible to perform the averaging operation by using only pixels in which pixels at point-symmetric positions about, for example, a watched pixel are combined and both are selected and thereby, it is possible to solve the problem that an averaged signal phase is deviated from an original position.
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公开(公告)号：EP1437886A4
公开(公告)日：2006-07-26
申请号：EP02775220
申请日：2002-09-20
Applicant: SONY CORP
Inventor： NAKAJIMA KEN , SATO NOBUYUKI , MITSUI SATOSHI
IPC: H04N5/232 , H04N5/235 , H04N5/335 , H04N5/341 , H04N5/345 , H04N5/378 , H04N9/04 , H04N9/07 , H04N101/00
CPC classification number: H04N5/3728 , H04N5/23293 , H04N5/2351 , H04N5/343 , H04N5/3456 , H04N5/3458 , H04N5/347 , H04N5/3651 , H04N9/045
Abstract: An imager comprising a solid-state imaging device of a large number of pixels and adapted for creating an image the quality of which can be adequately corrected. In a monitor reading mode, an imaging device (3) thins pixels, a camera system LSI (6) carries out detection of the image signal read out, a microcomputer (9) calculates a control value for image quality correction based on the detection data, and the camera system LSI (6) carries out image quality correction of the image signal on the basis of the control value. When the mode is changed to a capture reading mode, the camera system LSI (6) temporarily stores, in an image memory (7), the image signal of all the read pixels, reads out the image signal, and carries out detection. A microcomputer (9) calculates a control value on the basis of the detection data and the previous detection data in the monitor reading mode before the capture reading mode, the camera system LSI (6) thereafter reads out the image signal again, and the microcomputer (9) carries out image quality correction on the basis of the control value.
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公开(公告)号：EP1367536A4
公开(公告)日：2008-07-16
申请号：EP02703859
申请日：2002-02-20
Applicant: SONY CORP
Inventor： NAKAJIMA KEN , MITSUI SATOSHI
CPC classification number: G06T5/002 , G06T5/20 , G06T2207/20192
Abstract: The present invention relates to an image reduction method and apparatus to be preferably used to digitize and process, for example, an image signal. Therefore, in the case of the present invention, level values a to h of peripheral pixels of a pattern 1, the level value o of a watched pixel, and the value of a reference level &thetas; are input and level values a to h in which absolute values for differences between level values of peripheral pixels and the watched pixel are smaller than the value of the reference level &thetas; are output to output ports 3. Moreover, the value of the number of output ports 3 to which level values a to h is output to an output port 4. Moreover, the level value o of the watched pixel is supplied to a multiplier 9 and multiplied by an optional gain set value alpha , and the multiplication value is supplied to an adder 5 and added with the level values a to h output from the output ports 3 of a selection circuit 2 and the addition value is supplied to a divider 7. Furthermore, the gain set value alpha is supplied to an adder 11 and added with a value output from the output port 4 of the selection circuit 2 and the addition value is supplied to the divider 7. Then, a value output from the adder 5 is divided by a value output from the adder 11 and the value of the operation result is derived from an output port 8. Thereby, the degree of signal processing is optionally set by the so-called epsilon -filter and the rate of watched pixels relating to the averaging operation is controlled and thereby, it is possible to optionally set the degree of signal processing and perform optimum image processing.
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公开(公告)号：EP1291821A4
公开(公告)日：2003-07-02
申请号：EP02703858
申请日：2002-02-20
Applicant: SONY CORP
Inventor： NAKAJIMA KEN , MITSUI SATOSHI
CPC classification number: G06T5/20 , G06T5/002 , G06T2207/20192
Abstract: The present invention relates to an image noise reduction method and apparatus to be preferably used to digitize and process, for example, an image signal. Therefore, in the case of the present invention, level values a to h of peripheral pixels and the level value o of a watched pixel are respectively input to, for example, eight comparators 11 and the value "1" is output when absolute values of differences between the level values are smaller than the value of a reference level &thetas;. Moreover, peripheral pixels at point-symmetric positions about the watched pixel o are combined and signals output from the comparators 11 are supplied to four AND circuits 12 in accordance with combinations. Then, signals output from the AND circuits 12 are supplied to eight AND gates 13 in accordance with each combination and level values a to h of corresponding peripheral pixels are output to output ports 3 through the AND gates 13 when signals output from the AND circuits 12 respectively have the value "1". Moreover, signals output from the AND circuits 12 are supplied to an adder 14, the addition output is doubled by a multiplier 15, and the value "1" is added to the multiplication value and output to an output port 4. Thereby, it is possible to perform the averaging operation by using only pixels in which pixels at point-symmetric positions about, for example, a watched pixel are combined and both are selected and thereby, it is possible to solve the problem that an averaged signal phase is deviated from an original position.
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Patent Agency Ranking
公开(公告)号：JP2000056852A
公开(公告)日：2000-02-25
申请号：JP23040398
申请日：1998-08-17
Applicant: SONY CORP
Inventor： MITSUI SATOSHI , NAKAJIMA TAKESHI
Abstract: PROBLEM TO BE SOLVED: To provide a digital converting circuit capable of drastically reducing the storage capacity for the same conversion characteristics without remarkably inceasing the storage capacity of a storage circuit even when the number of bits of an address line is increased and being used for a gamma correcting circuit. SOLUTION: This circuit is provided with an AND gate 102 which separates an input digital signal to the high-order and low-order bits, stores a RAM module 100 with a converted digital signal corresponding to the high-order bits and a correction value for the converted digital signal as data, and selects a converted digital signal correction value between a converted digital signal read out when the high-order bits are inputted as an address to the RAM module 100 and the converted digital signal correction value with the low-order one bit of the input digital signal and an adder 101 which adds the output of the AND gate 102 the converted digital signal, and the output of this adder 101 is regarded as the output of the digital converting circuit.
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公开(公告)号：JP2002259962A
公开(公告)日：2002-09-13
申请号：JP2001050909
申请日：2001-02-26
Applicant: SONY CORP
Inventor： NAKAJIMA TAKESHI , MITSUI SATOSHI
Abstract: PROBLEM TO BE SOLVED: To resolve a problem of an equalized signal phase shifting from an original position. SOLUTION: For example, level values a to h of peripheral picture elements and a level value o of a target picture element are respectively inputted in eight comparators 11, and when the absolute value of the difference between the level values is smaller than a reference level θ, a value of '1' is outputted. Peripheral picture elements in point symmetrical positions with the target picture element o in the center are combined and signals from the comparators 11 are supplied to four AND circuits 12 in accordance with combinations. Signals from the AND circuits 12 are supplied to eight AND gates 13 in accordance with respective combinations, and when a signal from an AND circuit 12 is a value of '1', the level value a to h of a corresponding peripheral picture element is outputted to an output port 3 through the AND gate 13. The signal from the AND circuit 12 is supplied to an adder 14, the summed output is doubled at a multiplier 15, the multiplied output is added with a value of '1' at an adder 16, and it is outputted to an output port 4.
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公开(公告)号：JPH11284896A
公开(公告)日：1999-10-15
申请号：JP8151798
申请日：1998-03-27
Applicant: SONY CORP
Inventor： MITSUI SATOSHI
Abstract: PROBLEM TO BE SOLVED: To allow the device to have provision for both the NTSC and PAL systems while a scale of the device, power consumption and cost are reduced. SOLUTION: A timing generating section 18 uses a crystal vibrator 19 to generate a signal of a horizontal frequency in compliance with both the NTSC and PAL systems. Thus, in the case of selecting the PAL system, a CCD 11 outputs each of line data while including one pause line to 5 lines each. A 5:6 conversion section 14 synthesizes sequentially preceding and succeeding line data at a prescribed rate to generate data by 6 lines from the data by 5 lines.
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公开(公告)号：JP2002259965A
公开(公告)日：2002-09-13
申请号：JP2001050908
申请日：2001-02-26
Applicant: SONY CORP
Inventor： NAKAJIMA TAKESHI , MITSUI SATOSHI
Abstract: PROBLEM TO BE SOLVED: To arbitrarily set the degree of signal processing in an ε-filter. SOLUTION: Level values a to h of peripheral picture elements of figure 1, a level value o of a target picture element, and a value of a reference level θare inputted, and level values a to h of peripheral picture elements with absolute values of differences to the level value of the target picture element smaller than the value of the reference level θ are outputted to output ports 3. A value of the number of output ports 3 outputted with the level values a to h is outputted to an output port 4. The level value o of the target picture element is supplied to a multiplier 9 and it is multiplied with a random gain set value α, the multiplied value is supplied to an adder 5 and it is added with the level values a to h from the output ports 3 of a selecting circuit 2, and the added value is supplied to an analog divider 7. The gain set value αis supplied to an adder 11 and it is added with a value from the output port 4 of the selecting circuit 2, and the added value is supplied to the analog divider 7. The value from the adder 5 is divided by the value from the adder 11, and a value of its calculation result is fetched into an output port 8.
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公开(公告)号：JPH11285014A
公开(公告)日：1999-10-15
申请号：JP8454798
申请日：1998-03-30
Applicant: SONY CORP
Inventor： NAKAJIMA TAKESHI , MITSUI SATOSHI
Abstract: PROBLEM TO BE SOLVED: To obtain the image pickup device where image distortion such as jaggy is reduced without causing a large change in the configuration of a conventional signal processing circuit. SOLUTION: A chrominance processing circuit 10 applies chroma processing to color pixel data from a CCD and provides an output of a chroma signal. Furthermore, a luminance processing circuit 15 applies luminance processing to the pixel data and provides an output of a luminance signal. A multiplier 3 multiplies a correction coefficient to cancel modulation by a color filter with each pixel of the input signal at a pre-stage of the chrominance processing circuit 10 and the luminance processing circuit 15. A switch 17 selects each correction coefficient set in advance for each color component in registers 16. Moreover, multipliers 8,12 multiply a correction coefficient that is a reciprocal to the correction coefficient for the multiplier 3 with the chrominance signal for the chrominance processing circuit 10, which can conduct chrominance signal processing equal to conventional processing.
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