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公开(公告)号：DE68919302D1
公开(公告)日：1994-12-15
申请号：DE68919302
申请日：1989-08-23
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU , ENDO KATSUMI , MIURA TORU
Abstract: A video recording apparatus having a built-in type camera which includes an imager (10) for picking up an object and a recorder (20) for recording a video signal derived from the imager (10) in accordance with a predetermined format having an analog-to-digital converter (11) for converting the video signal from the image to digital image data, a memory (13) for storing the digital image data, a converting circuit (15) for converting the image data read out from the memory (13) to an image signal, a superimposing circuit (5,6,7) for superimposing the image signal formed of the image data upon the video signal from the imager (10), a control circuit (12) for controlling the writing and reading of the image data in the memory (13), a first operation switch (31) for causing the control circuit to store the image data in the memory (13), a second operation switch (32) for causing the control circuit (12) to superimpose the image signal upon the video signal, and a third operation switch (33) causing the control circuit (12) to designate the color of the image signal, wherein when the second operation switch (32) is in its OFF-state, the third operation switch (33) is operated as a selection switch of other camera mode functions.
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公开(公告)号：DE68919302T2
公开(公告)日：1995-04-06
申请号：DE68919302
申请日：1989-08-23
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU , ENDO KATSUMI , MIURA TORU
Abstract: A video recording apparatus having a built-in type camera which includes an imager (10) for picking up an object and a recorder (20) for recording a video signal derived from the imager (10) in accordance with a predetermined format having an analog-to-digital converter (11) for converting the video signal from the image to digital image data, a memory (13) for storing the digital image data, a converting circuit (15) for converting the image data read out from the memory (13) to an image signal, a superimposing circuit (5,6,7) for superimposing the image signal formed of the image data upon the video signal from the imager (10), a control circuit (12) for controlling the writing and reading of the image data in the memory (13), a first operation switch (31) for causing the control circuit to store the image data in the memory (13), a second operation switch (32) for causing the control circuit (12) to superimpose the image signal upon the video signal, and a third operation switch (33) causing the control circuit (12) to designate the color of the image signal, wherein when the second operation switch (32) is in its OFF-state, the third operation switch (33) is operated as a selection switch of other camera mode functions.
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公开(公告)号：DE69114972T2
公开(公告)日：1996-04-18
申请号：DE69114972
申请日：1991-09-10
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU , KOKUBO YUJI
IPC: H04N5/235 , H04N5/335 , H04N5/341 , H04N5/351 , H04N5/353 , H04N5/369 , H04N5/372 , H04N5/378 , H04N3/15 , H04N5/238
Abstract: A solid-state imaging apparatus includes a solid-state imaging device (11) having its charge accumulation time controllable by controlling the draining timing of accumulated charges, a level detecting device (15) for detecting an output level of the device (11), and a controlling device (18) for controlling the charge accumulating time of the device (11) based on an output of the level detecting device (15).
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公开(公告)号：DE69114972D1
公开(公告)日：1996-01-11
申请号：DE69114972
申请日：1991-09-10
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU , KOKUBO YUJI
IPC: H04N5/235 , H04N5/335 , H04N5/341 , H04N5/351 , H04N5/353 , H04N5/369 , H04N5/372 , H04N5/378 , H04N3/15 , H04N5/238
Abstract: A solid-state imaging apparatus includes a solid-state imaging device (11) having its charge accumulation time controllable by controlling the draining timing of accumulated charges, a level detecting device (15) for detecting an output level of the device (11), and a controlling device (18) for controlling the charge accumulating time of the device (11) based on an output of the level detecting device (15).
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公开(公告)号：JPH07154750A
公开(公告)日：1995-06-16
申请号：JP32325893
申请日：1993-11-29
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU
IPC: H04N7/01
Abstract: PURPOSE:To enable the use of a general-purpose field memory unnecessitating any special circuit and many elements by writing image data in the prescribed area of a valid picture composed of a first video signals into a field memory and reading these data as second video signals. CONSTITUTION:In order to transform the luminance signal of a PAL system to the luminance signal of an NTSC system, the format transforming circuit is constituted as follows; namely, it is composed of an input terminal 1 for supplying an analog luminance signal SA1 of the PAL system, A/D converter 2 of 8 bits for inputting one sample, field memory 3, D/A converter 4 and output terminal 6 for outputting an analog luminance signal SA2 of the NTSC system. The memory 3 performs the write and read of data in a dual port form respectively corresponding to independent clocks, and the permission/inhibition can be arbitrarily controlled by the memory 3. Namely, the write of a first video signal SD1 is permitted, and a second video signal SD2 is read as a synchronizing signal.
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Patent Agency Ranking
公开(公告)号：JPH06217207A
公开(公告)日：1994-08-05
申请号：JP541293
申请日：1993-01-14
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU
Abstract: PURPOSE:To improve the precision and stability of a shutter speed. CONSTITUTION:A high-speed counter 21 counts a clock of frequency much higher than the frequency of a horizontal synchronizing signal. A low-speed counter 25 counts a clock of the same frequency with the horizontal synchronizing signal. A logarithmic converting ROM 30 logarithmically converts data corresponding to the charge storage time of a CCD on addresses and outputs count control data. A comparator 23 compares the count control data with the count output data of the high-speed counter 21. A comparator 27 compares the count control data with the count output data of the low-speed counter 25. An AND gate 28 ANDs the comparison output of the comparator 27 with a pulse RP. A NOR gate 29 puts the output of the AND gate 29 and the comparison output of the comparator 23 together.
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公开(公告)号：JPH0257088A
公开(公告)日：1990-02-26
申请号：JP20909288
申请日：1988-08-23
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU , ENDO KATSUMI , MIURA TORU
Abstract: PURPOSE:To obtain multiple additional functions with a single operation switch by using with switching a third operation switch in accordance with the operation of a second operation switch and making the third operation switch into a switch to select another function when the second operation switch is under an off state. CONSTITUTION:A title device is provided with an A/D conversion circuit 11 to form image data, a memory 13 to store the image data, a conversion circuit 15 to form an image signal through the image data to be read out from the memory 13, a titler circuit 12 to control the read and write of the image data for the memory 13, a first operation switch 31 which generates operation information to store the image data into the memory 13 for the titler circuit 12, a second operation switch 32 which generates the operation information to insert the image signal into a video signal for the titler circuit 12 and a third operation 33 which generates the operation information to specify the color of the image signal for the titler circuit 12. When the second operation switch 32 is under the off state, it is constituted to use the third switch 33 as the selection switch of another function.
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公开(公告)号：JP2007036651A
公开(公告)日：2007-02-08
申请号：JP2005216807
申请日：2005-07-27
Inventor： NAKAJIMA TAKATSUGU
IPC: H04N5/225
Abstract: PROBLEM TO BE SOLVED: To provide a camera apparatus advantageous of effectively suppressing spurious radiation.
SOLUTION: A static capacitance is formed between a first slide electrode 50 and a base member 10 by facing the first slide electrode 50 with the base member 10 with a paint layer 1004 inbetween in a state that the first slide electrode 50 electrically connected to a first chassis 22 is in slide contact with the base member 10. Similarly, a static capacitance is formed between a second slide electrode 60 and a second chassis 32 by facing the second slide electrode 60 with the second chassis 32 with a paint layer 3204 inbetween in a state that the second slide electrode 60 electrically connected to the first chassis 22 is in slide contact with the second chassis 32.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：提供有效抑制杂散辐射的相机装置。 解决方案：在第一滑动电极50和基座部件10之间通过面对第一滑动电极50与第一滑动电极50与底座部件10之间形成静电电容，涂覆层1004在其之间，第一滑动电极50电连接 第一底盘22与基部构件10滑动接触。类似地，通过面对第二滑动电极60而在第二滑动电极60和第二机架32之间形成静电容，第二机架32具有涂层3204 电连接到第一底盘22的第二滑动电极60与第二机架32滑动接触的状态。（C）2007年，JPO和INPIT
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9.发明专利Imaging system, imaging control unit, vertical synchronization method, and program 有权成像系统，成像控制单元，垂直同步方法和程序
公开(公告)号：JP2006332803A
公开(公告)日：2006-12-07
申请号：JP2005150064
申请日：2005-05-23
Inventor： NAKAJIMA TAKATSUGU
CPC classification number: H04N5/0733
Abstract: PROBLEM TO BE SOLVED: To achieve external synchronization automatically without any phase adjustment, and to extend the transmission line between an imaging apparatus and an imaging control unit without any limitation.
SOLUTION: An imaging system comprises the imaging apparatus 100 that photographs an object and generates an image signal, and the imaging control unit 110 connected to the imaging apparatus via the transmission line. The imaging apparatus has a vertical synchronization generation circuit 200 for generating an internal vertical synchronization signal utilized for imaging in the imaging apparatus. The imaging control unit has: a delay measurement circuit 210 for measuring the amount of delay between a test signal outputted to the imaging apparatus and the test signal outputted to the imaging apparatus, and going back the transmission line; and a vertical synchronization phase advancing circuit 214 that advances the phase of an external vertical synchronization signal by the amount of delay for outputting to the imaging apparatus. The vertical synchronization generation circuit is reset by a signal outputted from the vertical synchronization phase advancing circuit.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：在没有任何相位调整的情况下自动实现外部同步，并且在成像设备和成像控制单元之间扩展传输线而没有任何限制。 解决方案：成像系统包括拍摄对象并生成图像信号的成像装置100，以及经由传输线连接到成像装置的成像控制单元110。 成像装置具有垂直同步产生电路200，用于产生用于在成像装置中成像的内部垂直同步信号。 成像控制单元具有：延迟测量电路210，用于测量输出到成像装置的测试信号与输出到成像装置的测试信号之间的延迟量，并返回传输线; 以及垂直同步相位提前电路214，其将外部垂直同步信号的相位推迟到用于输出到成像装置的延迟量。 垂直同步产生电路由从垂直同步相位提前电路输出的信号复位。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JPH11168672A
公开(公告)日：1999-06-22
申请号：JP33186397
申请日：1997-12-02
Applicant: SONY CORP
Inventor： NAKAJIMA TAKATSUGU
Abstract: PROBLEM TO BE SOLVED: To generate a timing pulse so as not to generate a fixed pattern noise(FPN) in an image signal which is outputted from a CCD image sensor. SOLUTION: A timing generator 16 generates a horizontal drive pulse for driving the horizontal register of a CCD image sensor 11. Since a level shift circuit 21 generates a clamp pulse based on the horizontal drive pulse, the clamp pulse is generated corresponding to the phase modulation of the horizontal drive pulse.
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