公开(公告)号：WO2006088881A3

公开(公告)日：2007-01-18

申请号：PCT/US2006005204

申请日：2006-02-14

Applicant: IBM ,  SONY CORP ,  NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

IPC: H01L21/31

CPC classification number: H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter "SiCOH") in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, -CH 2 - crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH 3 +CH 2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH 3 bonding of greater than about 2.0, and a peak area for Si-O-Si bonding of greater than about 60%, and a porosity of greater than about 20%.

Abstract translation: 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和更少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3 N 2 CH 2拉伸峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：WO2007027762A3

公开(公告)日：2008-01-24

申请号：PCT/US2006033841

申请日：2006-08-30

Applicant: SONY CORP ,  SONY ELECTRONICS INC ,  NOGAMI TAKESHI ,  INOUE KEISHI

Inventor： NOGAMI TAKESHI ,  INOUE KEISHI

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two. The layout of lines in the second level of metallization is arranged so that they partially overlap in the vertical direction one of the lines in the first level of metallization.

Abstract translation: 提供了一种用于设计具有相对于预先存在的互连结构布局具有减小的横向尺寸的互连结构的集成电路的方法。 该方法首先通过将给定的金属化水平的每条导线的宽度减小到规定的宽度，从而将预定的互连结构布局中给定的金属化水平的横向尺寸减小所需的量。 导电线被电介质材料分开。 互连结构布局中给定的金属化水平被划分为至少第一级和第二级的金属化，通过在给定级别的第二级别的金属化交替的线中排列。 每条线的横向上的规定宽度在第一和第二金属化水平上增加至少两倍。 在第二级金属化中的线的布局布置成使得它们在第一级金属化中的一条线上的垂直方向上部分重叠。

公开(公告)号：WO2007126956A3

公开(公告)日：2008-08-14

申请号：PCT/US2007007770

申请日：2007-03-28

Applicant: SONY CORP ,  SONY ELECTRONICS INC ,  MIYATA KOJI ,  NOGAMI TAKESHI

Inventor： MIYATA KOJI ,  NOGAMI TAKESHI

IPC: H01L21/4763

CPC classification number: H01L21/76826 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/31695 ,  H01L21/76807

Abstract: A method is provided for fabricating a damascene interconnection The method begins by forming on a substrate (100) a porous dielectric layer (130) and imparting a porogen material into an upper portion of the porous dielectric layer to define a less porous dielectric sublayer (130a) within the dielectric layer A capping layer (140) is formed on the less porous dielectric sublayer and a resist pattern (145) is formed over the capping layer to define a first interconnect opening (150) The capping layer and the dielectric layer ar etched through the resist pattern to form the first interconnect opening The resist pattern is removed and an interconnection is formed by filling the first interconnect opening with conductive material (165) The interconnection is planapzed to remove excess conductive material

Abstract translation: 提供一种用于制造镶嵌互连的方法。该方法开始于在基底（100）上形成多孔介电层（130）并将致孔剂材料赋予多孔介电层的上部以限定较少多孔的介电子层（130a ）覆盖层（140）形成在较少多孔的介电子层上，并且在封盖层上形成抗蚀剂图案（145）以限定第一互连开口（150）。覆盖层和电介质层被蚀刻 通过抗蚀剂图案形成第一互连开口去除抗蚀剂图案，并且通过用导电材料（165）填充第一互连开口形成互连。互连被平面化以除去过量的导电材料

公开(公告)号：WO2007027762A8

公开(公告)日：2007-12-06

申请号：PCT/US2006033841

申请日：2006-08-30

Applicant: SONY CORP ,  SONY ELECTRONICS INC ,  NOGAMI TAKESHI ,  INOUE KEISHI

Inventor： NOGAMI TAKESHI ,  INOUE KEISHI

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two. The layout of lines in the second level of metallization is arranged so that they partially overlap in the vertical direction one of the lines in the first level of metallization.

Abstract translation: 提供了一种用于设计具有相对于预先存在的互连结构布局具有减小的横向尺寸的互连结构的集成电路的方法。 该方法首先通过将给定的金属化水平的每条导线的宽度减小到规定的宽度，从而将预定的互连结构布局中给定的金属化水平的横向尺寸减小所需的量。 导电线被电介质材料分开。 互连结构布局中给定的金属化水平被划分为至少第一级和第二级的金属化，通过在给定级别的第二级别的金属化交替的线中排列。 每条线的横向上的规定宽度在第一和第二金属化水平上增加至少两倍。 在第二级金属化中的线的布局布置成使得它们在第一级金属化中的一条线上的垂直方向上部分重叠。

公开(公告)号：DE60113574D1

公开(公告)日：2006-02-09

申请号：DE60113574

申请日：2001-02-12

Applicant: SONY CORP

Inventor： KOMAI NAOKI ,  SEGAWA YUJI ,  NOGAMI TAKESHI

IPC: H01L21/3205 ,  C23C18/16 ,  H01L21/28 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: A process for fabricating a semiconductor device, which comprises forming, on a metal wiring formed from copper or a copper alloy, a barrier film which functions as a diffusion-preventing film for the metal wiring by an electroless plating method, wherein a catalytic metal film which serves as a catalyst in the electroless plating method is selectively formed on the metal wiring by a displacement plating method using a displacement plating solution at a temperature in the range of 30 DEG C or more and lower than a boiling point thereof, and the barrier film is selectively formed on the catalytic metal film by the electroless plating method. It is an object of the present invention, to selectively and uniformly carry out the catalyst activation to the surface of the metal wiring made of copper or a copper alloy by using palladium so as to improve plating property of the electroless plating method using a hypophosphite as a reducing agent and the reliability of the wiring.

公开(公告)号：EP1849183A4

公开(公告)日：2010-09-01

申请号：EP06735050

申请日：2006-02-14

Applicant: IBM ,  SONY CORP

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

IPC: H01L21/31

CPC classification number: H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

公开(公告)号：DE60113574T2

公开(公告)日：2006-06-22

申请号：DE60113574

申请日：2001-02-12

Applicant: SONY CORP

Inventor： KOMAI NAOKI ,  SEGAWA YUJI ,  NOGAMI TAKESHI

IPC: H01L21/3205 ,  H01L21/768 ,  C23C18/16 ,  H01L21/28 ,  H01L21/288 ,  H01L23/52 ,  H01L23/532

Abstract: A process for fabricating a semiconductor device, which comprises forming, on a metal wiring formed from copper or a copper alloy, a barrier film which functions as a diffusion-preventing film for the metal wiring by an electroless plating method, wherein a catalytic metal film which serves as a catalyst in the electroless plating method is selectively formed on the metal wiring by a displacement plating method using a displacement plating solution at a temperature in the range of 30 DEG C or more and lower than a boiling point thereof, and the barrier film is selectively formed on the catalytic metal film by the electroless plating method. It is an object of the present invention, to selectively and uniformly carry out the catalyst activation to the surface of the metal wiring made of copper or a copper alloy by using palladium so as to improve plating property of the electroless plating method using a hypophosphite as a reducing agent and the reliability of the wiring.

公开(公告)号：JP2004273790A

公开(公告)日：2004-09-30

申请号：JP2003062914

申请日：2003-03-10

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HORIKOSHI HIROSHI ,  SEGAWA YUJI ,  NOGAMI TAKESHI

IPC: C23C18/18 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To enhance reliability of wiring by enhancing deposition selectivity of a catalytic metal layer being formed when a cap barrier layer is formed on the surface of a metallization and reducing damage on the metallization when the catalytic metal layer is deposited.
SOLUTION: In the process for fabricating a semiconductor device comprising steps for forming a catalytic metal layer 17 by immersion plating only on a metallization 16 formed on an insulating film 12 on a substrate 11 and for forming a cap barrier layer 18 selectively on the metallization 16 by electroless plating utilizing the catalytic metal layer 17, the step for forming the catalytic metal layer 17 by immersion plating employs such a catalytic plating liquid as the ζ-potential on the insulating film 12 and the ζ-potential on the metallization 16 have different polarities. In order to reduce damage on the metallization, concentration of palladium in a palladium immersion plating liquid being used in immersion plating for forming the catalytic metal layer and the etching amount of metal are optimized.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：为了提高布线的可靠性，当在金属化表面上形成帽阻挡层时，提高催化金属层的沉积选择性，并且当催化金属层沉积时减少对金属化的损伤 。 解决方案：在制造半导体器件的方法中，包括以下步骤：通过仅在形成在衬底11上的绝缘膜12上的金属化层16上浸渍形成催化金属层17，并且选择性地形成帽阻挡层18 通过使用催化金属层17的无电镀处理金属化16，通过浸镀形成催化金属层17的步骤使用这样的催化镀液作为绝缘膜12上的ζ电位和金属化16上的ζ电位 具有不同的极性。 为了减少对金属化的损害，优化了用于形成催化金属层的浸镀中的钯浸镀液中的钯浓度和金属的蚀刻量。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004230505A

公开(公告)日：2004-08-19

申请号：JP2003021360

申请日：2003-01-30

Applicant: Sony Corp ,  ソニー株式会社

Inventor： SATO SHUZO ,  NOGAMI TAKESHI ,  KOMAI HISANORI ,  YASUDA YOSHIYA ,  OTORII SUGURU ,  TAKAHASHI SHINGO ,  HORIKOSHI HIROSHI ,  TAI KAORI

IPC: B23H5/08

Abstract: PROBLEM TO BE SOLVED: To provide a control method of an electrolytic polishing pad for certainly and favorably polishing an article even in a case of doing it in combination of CMP and electrolytic polishing. SOLUTION: This is the control method of the electrolytic polishing pad 3 used by being pressed and slid on the polishing article 1 and constituted to electrify an electrolytic electric current for electrolytic polishing in an electrolytic solution, and it detects lowering of a polishing rate of the electrolytic polishing pad 3 in accordance with a friction coefficient μ provided by monitoring or a change of electric resistance R by monitoring the friction coefficient μ between the polishing article 1 and the electrolytic polishing pad 3 or the electric resistance R at the time of the electrolytic polishing pad 3 electrifying the electrolytic electric current. Additionally, the polishing rate is recovered by a mechanical polishing process, a chemical polishing process or an electric polishing process applied on a surface of the electrolytic polishing pad 3 in case of detecting lowering of the polishing rate. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004200273A

公开(公告)日：2004-07-15

申请号：JP2002364780

申请日：2002-12-17

Applicant: Sony Corp ,  ソニー株式会社

Inventor： SEGAWA YUJI ,  HORIKOSHI HIROSHI ,  NOGAMI TAKESHI ,  SATO SHUZO ,  YASUDA YOSHIYA ,  ISHIHARA SHIGEO

IPC: C23C18/31 ,  C23C18/52 ,  H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a copper interconnect line having a CoWP based barrier film and exhibiting electromigration tolerance by depositing the CoWP based barrier film uniformly on the surface of the copper interconnect line without generating any void in the copper interconnect line.
SOLUTION: The process for fabricating a semiconductor device comprises a step for depositing a barrier film 32 selectively on a second interconnect line 25 by electroless plating utilizing a catalyst metallization layer 31 after it is formed, by substitution plating, only on the interconnect line (second interconnect line 25) formed of copper or a copper alloy on a substrate. The electroless plating liquid contains a first reducing agent requiring the catalyst metallization layer 31 when electroless plating reaction is started and a second reducing agent not requiring the catalyst metallization layer when electroless plating reaction is started and exhibiting a stronger reducing power than the first reducing agent.
COPYRIGHT: (C)2004,JPO&NCIPI