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公开(公告)号：DE69020756D1
公开(公告)日：1995-08-17
申请号：DE69020756
申请日：1990-03-02
Applicant: SONY CORP
Inventor： SHINKAI HIROYUKI , WACHI SHIGEAKI , TOSAKA SUSUMU , OKAWA SUMIHIRO
IPC: G11B7/00 , G11B7/004 , G11B7/0045 , G11B7/0055 , G11B7/085 , G11B7/09 , G11B7/125 , G11B19/04 , G11B27/36
Abstract: The present invention relates to an optical recording and reproducing apparatus comprising an erroneous recording prevention means which prevents this apparatus from making an erroneous recording or erasing operation while it records data on a writable disk (1). The apparatus is arranged such that, while it is performing a recording or erasing operation, a state of its beam of light just about to go off the control point of tracking and a state of its beam of light just about to go off the control point of focusing are each monitored and, when either of the states is detected, the recording or erasing operation is canceled. Hence, laser power of the beam of light can be controlled before the beam of light completely goes off the control point of tracking, thereby preventing the beam of light from affecting data having been recorded along other tracks.
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公开(公告)号：CA2232624A1
公开(公告)日：1998-01-29
申请号：CA2232624
申请日：1997-07-18
Applicant: SONY CORP
Inventor： NAKAMURA AKIRA , FUJIMORI TAKAHIRO , TAKIZUKA HIROSHI , OKAWA SUMIHIRO
Abstract: Arbitration signals and packet data are transmitted and received as 5-bit code data through transmission blocks (6A and 6B) and receiving blocks (7A and 7B) by providing a conversion block (3) which converts the arbitration signals into 5-bit code data and subjects the packet data to 4-bit/5-bit conversion. With this constitution, the cable lengths between nodes in a digital serial data interface (for instance IEEE1394 High Performance Serial Bus Standard) which performs the arbitration of the bus usage priority before the data transfer are increased and a digital serial data interface apparatus which facilitates the long distance transmission can be realized.
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公开(公告)号：CA1315879C
公开(公告)日：1993-04-06
申请号：CA583450
申请日：1988-11-18
Applicant: SONY CORP
Inventor： WACHI SHIGEAKI , OKAWA SUMIHIRO
Abstract: A system and method for accessing tracks for an optical disc apparatus are disclosed in which when a light spot is jumped toward a target track, an acceleration pulse is applies across a fine tracking actuator to accelerate the fine tracking actuator for a predetermined period of time, a relative speed of the light spot to the tracks of the optical disc is detected though a detection of a period of a traverse signal outputted due to a movement of the fine tracking actuator, and a control signal corresponding to the relative speed is used to control the movement speed of the fine tracking actuator. Therefore, before the end of a track jump, a constant relative speed can be achieved such that a smooth tracking servo can be carried out. Consequently, an access time to access the target track can be shortened.
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公开(公告)号：DE69429032D1
公开(公告)日：2001-12-20
申请号：DE69429032
申请日：1994-05-27
Applicant: SONY CORP
Inventor： OKAWA SUMIHIRO
IPC: G06F3/06 , G05B19/414 , G06F3/08 , G11B7/09 , G11B7/095 , G11B19/02 , G11B21/10 , G06F9/46 , G06F9/40
Abstract: An optical disk apparatus in which data is stored in internal registers (21 - 25) of a digital signal processor (13) need not be saved and returned when a servo processing based on an interrupt processing routine is executed. Internal registers of the digital signal processor are allocated. At least one group of the divided internal registers is exclusively allocated to the execution of a servo signal processing interrupt routine and the other groups of internal registers are exclusively allocated to execute a system control processing. With such allocations, when a sampling interrupt occurs, servo signal processing of a focus servo signal processing and a tracking servo processing is carried out without saving data from the internal registers of the digital signal processor. After servo processing is completed, the interrupt processing routine can be ended without returning data to the internal registers.
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Patent Agency Ranking
公开(公告)号：DE69020756T2
公开(公告)日：1995-12-07
申请号：DE69020756
申请日：1990-03-02
Applicant: SONY CORP
Inventor： SHINKAI HIROYUKI , WACHI SHIGEAKI , TOSAKA SUSUMU , OKAWA SUMIHIRO
IPC: G11B7/00 , G11B7/004 , G11B7/0045 , G11B7/0055 , G11B7/085 , G11B7/09 , G11B7/125 , G11B19/04 , G11B27/36
Abstract: The present invention relates to an optical recording and reproducing apparatus comprising an erroneous recording prevention means which prevents this apparatus from making an erroneous recording or erasing operation while it records data on a writable disk (1). The apparatus is arranged such that, while it is performing a recording or erasing operation, a state of its beam of light just about to go off the control point of tracking and a state of its beam of light just about to go off the control point of focusing are each monitored and, when either of the states is detected, the recording or erasing operation is canceled. Hence, laser power of the beam of light can be controlled before the beam of light completely goes off the control point of tracking, thereby preventing the beam of light from affecting data having been recorded along other tracks.
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公开(公告)号：DE69429032T2
公开(公告)日：2002-03-21
申请号：DE69429032
申请日：1994-05-27
Applicant: SONY CORP
Inventor： OKAWA SUMIHIRO
IPC: G06F3/06 , G05B19/414 , G06F3/08 , G11B7/09 , G11B7/095 , G11B19/02 , G11B21/10 , G06F9/46 , G06F9/40
Abstract: An optical disk apparatus in which data is stored in internal registers (21 - 25) of a digital signal processor (13) need not be saved and returned when a servo processing based on an interrupt processing routine is executed. Internal registers of the digital signal processor are allocated. At least one group of the divided internal registers is exclusively allocated to the execution of a servo signal processing interrupt routine and the other groups of internal registers are exclusively allocated to execute a system control processing. With such allocations, when a sampling interrupt occurs, servo signal processing of a focus servo signal processing and a tracking servo processing is carried out without saving data from the internal registers of the digital signal processor. After servo processing is completed, the interrupt processing routine can be ended without returning data to the internal registers.
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公开(公告)号：SG77717A1
公开(公告)日：2001-01-16
申请号：SG1999005109
申请日：1999-10-14
Applicant: SONY CORP
Inventor： NIWA YOSHIKATSU , OKAWA SUMIHIRO , NAKAMURA AKIRA , TAKIZUKA HIROSHI , FUJIMORI TAKAHIRO
Abstract: An interfacing device in which speed negotiation can be correctly realized without the necessity of becoming conscious of the real operating speed capability. To this end, the interfacing device includes a speed negotiation processing block 12 for selecting the data transfer speed (operating speed), a speed signal detection block 3A whether or not data received from outside is a speed signal representing the transfer speed. and a speed signal transmission block 3B for transmitting a speed signal based on the information received from the speed negotiation processing block 12. When the speed signal detection block 3A has detected that an operating speed higher than an allowed maximum operating speed has been selected, the speed negotiation processing block 12 again performs negotiation processing as it lowers the maximum operating speed one step each time negotiation processing is performed once or plural times.
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公开(公告)号：CA2286255A1
公开(公告)日：2000-04-16
申请号：CA2286255
申请日：1999-10-14
Applicant: SONY CORP
Inventor： NIWA YOSHIKATSU , NAKAMURA AKIRA , OKAWA SUMIHIRO , TAKIZUKA HIROSHI , FUJIMORI TAKAHIRO
Abstract: An interfacing device in which speed negotiation can be correctly realized without the necessity of becoming conscious of the real operating speed capability. To this end, the interfacing device includes a speed negotiation processing block 12 for selecting the data transfer speed (operating speed), a speed signal detection block 3A whether or not data received from outside is a speed signal representing the transfer speed, and a speed signal transmission block 3B for transmitting a speed signal based on the information received from the speed negotiation processing block 12. When the speed signal detection block 3A has detected that an operating speed higher than an allowed maximum operating speed has been selected, the speed negotiation processing block 12 again performs negotiation processing as it lowers the maximum operating speed one step each time negotiation processing is performed once or plural times.
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公开(公告)号：EP0868048A4
公开(公告)日：2001-12-05
申请号：EP97930848
申请日：1997-07-18
Applicant: SONY CORP
Inventor： OKAWA SUMIHIRO , NAKAMURA AKIRA , TAKIZUKA HIROSHI , FUJIMORI TAKAHIRO
CPC classification number: H04L12/40078 , G06F13/385 , H04L12/40058 , H04L12/40084 , H04L25/4906
Abstract: Arbitration signals and packet data are transmitted and received as 5-bit code data through transmission blocks (6A and 6B) and receiving blocks (7A and 7B) by providing a conversion block (3) which converts the arbitration signals into 5-bit code data and subjects the packet data to 4-bit/5-bit conversion. With this constitution, the cable lengths between nodes in a digital serial data interface (for instance IEEE1394 High Performance Serial Bus Standard) which performs the arbitration of the bus usage priority before the data transfer are increased and a digital serial data interface apparatus which facilitates the long distance transmission can be realized.
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