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公开(公告)号：JPH1168801A
公开(公告)日：1999-03-09
申请号：JP21962297
申请日：1997-08-14
Applicant: SONY CORP
Inventor： SATO SADAJI
Abstract: PROBLEM TO BE SOLVED: To provide the signal processing circuit which uses efficiently a serial interface bus. SOLUTION: In the case of sending a transport stream packet, a received stream packet is divided or synthesized based on a division number or a synthesis number set in advance depending on an input rate and suppresses jitter in a serial interface bus and stamps a time stamp deciding a data output time at a receiver side and sends the resulting packet to a serial interface bus BS by transmission processing circuits 106, 107 and a link core 101. Thus, a frequency band required for communication is suppressed and the frequency band of the serial bus BS is used efficiently.
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公开(公告)号：JP2007060727A
公开(公告)日：2007-03-08
申请号：JP2006327497
申请日：2006-12-04
Inventor： SATO SADAJI , AOKI TETSUYA , MUTO TAKAYASU
IPC: H04L29/10 , H04L12/28 , H04L12/801 , H04L12/841 , H04L12/911 , H04L29/08
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of automatically performing late processing of the transmission and achieving accurate packet transmission. SOLUTION: A post-transmission processing circuit 107A sets a LATE threshold LTH according to the fractions of the unit packets set in the CFR 111 by the CPU 30, decides from the relationship between a current time CT and the late threshold LTH whether or not a time stamp set by the pre-transmission processing circuit 106 and stored in a FIFO 110 is valid, transmits a packet when the time stamp is valid, and does not transmit it but processes the next packet when it is invalid. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：提供能够自动执行传输的后期处理并实现精确的分组传输的信号处理电路。 解决方案：后发送处理电路107A根据CPU30在CFR 111中设置的单位分组的分数来设置LATE阈值LTH，根据当前时间CT和晚期阈值LTH之间的关系来确定是否 或者由预先发送处理电路106设置并且存储在FIFO 110中的时间戳有效，当时间戳有效时发送分组，并且不发送分组，而是在无效时处理下一个分组。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2000156698A
公开(公告)日：2000-06-06
申请号：JP32997598
申请日：1998-11-19
Applicant: SONY CORP
Inventor： SATO SADAJI
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit that can extract only specific data and add information to the extracted data without the need for an externally mounted circuit. SOLUTION: In a plurality of application interface circuit 103A is provided with a PID filter 1031 that extracts specific stream data designated by a value set to a register PID of a CFR 114 from channel data of a digital satellite broadcast sent as transport stream data and a timing generating circuit 1032 that generates a timing signal S1032 to insert insert packet data to a stream data area not extracted from timing information of unselected stream data among a series of transport stream data and outputs the signal S1032 to an insert packet buffer 106. An insert packet is read from the insert packet buffer 106 by the timing signal S1032.
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公开(公告)号：JP2000156697A
公开(公告)日：2000-06-06
申请号：JP32997498
申请日：1998-11-19
Applicant: SONY CORP
Inventor： SATO SADAJI
IPC: H04N5/91 , G06F13/00 , G06F21/10 , H04L12/40 , H04L12/407 , H04N7/16 , H04N19/423 , H04N19/467 , H04N19/50 , H04N19/70 , H04N7/32
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit that can prevent illegal copy of digital data sent or received between different devices. SOLUTION: The signal processing circuit is provided with an encryption processing circuit 107 consisting of an encryption mode selection circuit 1071 that selects one encryption key mode among 6 encryption modes set to a CFR 114 by a CPU 30, of an encryption mode detection circuit 1072 that detects an encryption mode used for encrypting data based on encryption information added to a received packet and outputs the detection result to the encryption mode selection circuit 1071, and of an encryption engine circuit 1074 that encrypts transmission data based on an encryption key designated by the encryption mode selection circuit 1071 in the case of transmission and decodes encrypted data based on the encryption key designated by the encryption mode selection circuit 1071 in the case of receiving data, and with an after- transmission processing circuit 109 that sets encrypted information to a 1394-header to provide a prescribed transmission packet in the case of transmission.
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公开(公告)号：JPH10285236A
公开(公告)日：1998-10-23
申请号：JP8316197
申请日：1997-04-01
Applicant: SONY CORP
Inventor： SATO SADAJI
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit in which the circuit scale and the cost are reduced to relieve the load of the control system. SOLUTION: A processing circuit is provided with a resolver 105 that receives a 1st self ID packet sent through an IEEE 1394 serial bus BS in the case of bus reset, detects its gap count 'gap-cnt-1', detects a gap count gap-cnt N for each self-ID packet succeedingly, compares it with the 1st gap count gap-cnt 1, provides an output of a low level signal S105 to a CFR 111 when they are equal to each other and provides an output of a high level signal S105 to the CFR 111 when they are not equal to each other. A CPU 30 conducts bus reset by regarding it, e.g. that a new node is connected when receiving information denoting different gap count and the detected gap count is reported to the CPU 30 via the CFR 111.
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Patent Agency Ranking
公开(公告)号：JP2007151136A
公开(公告)日：2007-06-14
申请号：JP2006327500
申请日：2006-12-04
Inventor： SATO SADAJI , AOKI TETSUYA , MUTO TAKAYASU
IPC: H04L12/40 , G06F13/38 , H04L12/28 , H04L29/08 , H04N7/173 , H04N19/00 , H04N19/65 , H04N19/70 , H04N21/435 , H04N21/436
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of preventing a data loss or unwanted data from being output to an application side even when time information to be set in accordance with a data amount is changed. SOLUTION: When a data read control signal S1063 is actively received by a processing circuit 107 after transmission, it is decided that a data amount is increased to change into a short delay time, a read pointer is matched with a write pointer indicated by a storage information signal S106 and a new transmission packet with the data amount increased is read from a FIFO 110. Data to which a time stamp based on a delay time set before the increase in the data amount is added are reset and 1394 header, CIP header 1, 2 are added to the read packet to be output to the transmission circuit of a link core 111. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：即使当要根据数据量设置的时间信息改变时，提供能够防止数据丢失或不需要的数据被输出到应用侧的信号处理电路。 解决方案：当数据读取控制信号S1063在传输之后由处理电路107主动地接收时，确定数据量增加以变成短的延迟时间，读指针与指示的写指针相匹配 通过存储信息信号S106和从FIFO110读出数据量增加的新的发送分组被复位，并且添加了基于在数据量增加之前设置的延迟时间的时间戳的数据，并且1394报头， 将CIP标题1,2添加到读取的包中以输出到链接核心111的传输电路。（C）版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2007060728A
公开(公告)日：2007-03-08
申请号：JP2006327498
申请日：2006-12-04
Inventor： SATO SADAJI , AOKI TETSUYA , MUTO TAKAYASU
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of automatically performing late processing of the transmission and achieving accurate packet transmission. SOLUTION: A pre-reception processing circuit 108B outputs a stored information signal S108, which indicates that the received data has been stored in a FIFO 110, to a post-reception processing circuit 109B each time writing a packet and that the post-reception processing circuit 109B compares a time stamp data TS added to the received packet with a cycle time CT from an inner cycle counter and outputs the received data stored in the FIFO 110 when the cycle time CT is larger than the time stamp data TS (CT>TS). COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：提供能够自动执行传输的后期处理并实现精确的分组传输的信号处理电路。 解决方案：预接收处理电路108B每当写入分组时，将表示接收到的数据已经存储在FIFO110中的存储的信息信号S108输出到后接收处理电路109B， 接收处理电路109B将添加到接收到的分组的时间戳数据TS与来自内周期计数器的周期时间CT进行比较，并且当周期时间CT大于时间戳数据TS时，输出存储在FIFO 110中的接收数据 CT> TS）。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2000183913A
公开(公告)日：2000-06-30
申请号：JP36043598
申请日：1998-12-18
Applicant: SONY CORP
Inventor： SATO SADAJI
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit for transmitting protocol data whose synchronizing information should be multiplexed and transmitted to a serial interface bus based on a protocol. SOLUTION: This circuit is provided with a pre-transmission processing circuit 108 for generating 4 byte time stamp data obtained by adding a delay time set in a CFR 114 from a CPU 30 to a time when the 8th sample reaches, and storing the data in an FIFO 112 for transmission, and a post-transmission processing circuit 109 for operating late processing for preventing the transmission of a packet when the transmission of the packet becomes meaningless due to the time delay after the packet is transmitted to the reception side from a relationship between the value TS of the time stamp data stored in the FIFO 112 for transmission and the present time CT, and setting the time stamp data value in the SYT area of a CIP header 2 as synchronizing information only in the case of operating normal packet transmission without operating any late processing, and generating the transmission packet in a configuration in which the synchronizing information is multiplexed.
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公开(公告)号：JP2000156678A
公开(公告)日：2000-06-06
申请号：JP32997398
申请日：1998-11-19
Applicant: SONY CORP
Inventor： SATO SADAJI
IPC: G06F13/38 , G06F21/10 , H04L9/00 , H04L9/12 , H04L9/18 , H04L12/28 , H04L12/70 , H04L29/06 , H04N7/16 , H04L12/56
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit by which impossibility of decoding is prevented due to disabled discrimination of a plurality of encryption modes while preventing illegal copying and a receiver side can correctly decode received data. SOLUTION: The signal processing circuit is provided with an encryption mode continuity discrimination circuit 1091, which confirms continuity of an encryption mode in the case of reading transmission data consisting of a plurality of packets from an FIFO 112 and instructs a transmission circuit of a link core 101 to stop transmission of data when confirming discontinuity of the encryption mode even when there is a room for a frequency band for transmission of data in a transmission cycle in compliance with the 1394 standards and to transmit packets encrypted by a different encryption key for a succeeding cycle. Thus, data only encrypted by one encryption mode are transmitted within one cycle in compliance with the 1394 standards and data encrypted by a different encryption mode are transmitted for a succeeding cycle.
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公开(公告)号：JP2000134281A
公开(公告)日：2000-05-12
申请号：JP30609198
申请日：1998-10-27
Applicant: SONY CORP
Inventor： SATO SADAJI
Abstract: PROBLEM TO BE SOLVED: To generate a clock with a frequency in compliance with an application side and to obtain data that can be processed at the application side by converting a frequency of a system clock into a frequency in compliance with the specification of the application side so as to eliminate the need for separate provision of a read clock generating circuit at the outside of the circuit. SOLUTION: A reception pre-processing circuit 8 receives a communication packet transferred via a link core 101 and stores a source packet header and data to an FIFO 110. A reception post-processing circuit 109 receives a system clock SCLK fed from the link core 101 and converts its frequency into a frequency in compliance with the specification of an application side. Then packet data stored in the FIFO 110 are read based on the clock whose frequency is converted and the data are outputted to an MPEG transporter 40 as MPEG transport stream data via an application interface circuit 103.
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