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公开(公告)号：DE2610562A1
公开(公告)日：1976-09-30
申请号：DE2610562
申请日：1976-03-12
Applicant: SONY CORP
Inventor： SATO TERUO , MICHIHATA NOBUHARU
Abstract: A phase locked loop for use with a local oscillator includes a reference signal oscillator, a local oscillator the frequency of which is changed within a predetermined frequency range and a phase comparator for comparing output signals from the reference oscillator and the local oscillator. A low pass filter and a DC amplifier form a phase locked loop with the reference signal oscillator, local oscillator, and phase comparator. The gain of the DC amplifier is controlled in response to the frequency of the local oscillator so as to make its loop gain substantially constant. In accordance with one example of the invention, an FM feedback circuit is provided between the demodulated output side and the input side of the DC amplifier so as to improve the sensitivity of a receiver using the local oscillator.
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公开(公告)号：DE69330454T2
公开(公告)日：2002-04-18
申请号：DE69330454
申请日：1993-10-26
Applicant: SONY CORP
Inventor： SATO TERUO
Abstract: A Viterbi equalizer can provide an accurate equalizing characteristic. This Viterbi equalizer comprises a synchronizing signal data detecting circuit for detecting a synchronizing signal data portion from a reception signal data series, a transmission line characteristic estimating circuit for modelling an impulse response between a transmitter and a receiver by comparing a synchronizing signal data detected by the synchronizing signal data detecting circuit with a reference signal, and a decoding circuit for decoding a transmission data series by using a Viterbi algorithm on the basis of a transmission model obtained from the transmission line characteristic estimating circuit.
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公开(公告)号：DE69330454D1
公开(公告)日：2001-08-23
申请号：DE69330454
申请日：1993-10-26
Applicant: SONY CORP
Inventor： SATO TERUO
Abstract: A Viterbi equalizer can provide an accurate equalizing characteristic. This Viterbi equalizer comprises a synchronizing signal data detecting circuit for detecting a synchronizing signal data portion from a reception signal data series, a transmission line characteristic estimating circuit for modelling an impulse response between a transmitter and a receiver by comparing a synchronizing signal data detected by the synchronizing signal data detecting circuit with a reference signal, and a decoding circuit for decoding a transmission data series by using a Viterbi algorithm on the basis of a transmission model obtained from the transmission line characteristic estimating circuit.
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公开(公告)号：AU8738175A
公开(公告)日：1977-06-16
申请号：AU8738175
申请日：1975-12-09
Applicant: SONY CORP
Inventor： SATO TERUO , NAKAMURA HIDEO
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Patent Agency Ranking
公开(公告)号：DE69232647T2
公开(公告)日：2002-11-28
申请号：DE69232647
申请日：1992-03-19
Applicant: SONY CORP
Inventor： SATO TERUO
IPC: H03D3/00 , H04L27/22 , H04L25/03 , H04L27/227
Abstract: The present invention is directed to a differential phaseshift keying (PSK) signal demodulator in which an error rate provided when a signal modulated according to a pi /4-shift DQPSK modulation system is demodulated can be improved. The differential PSK signal demodulator includes means (4 to 10) for judging changing traces of signal points from outputs of an I-axis level discriminating device (1) and a Q-axis level discriminating device (2) to select an optimum path, thus making it possible to reduce a bit error rate (BER).
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公开(公告)号：DE69232647D1
公开(公告)日：2002-07-25
申请号：DE69232647
申请日：1992-03-19
Applicant: SONY CORP
Inventor： SATO TERUO
IPC: H03D3/00 , H04L27/22 , H04L25/03 , H04L27/227
Abstract: The present invention is directed to a differential phaseshift keying (PSK) signal demodulator in which an error rate provided when a signal modulated according to a pi /4-shift DQPSK modulation system is demodulated can be improved. The differential PSK signal demodulator includes means (4 to 10) for judging changing traces of signal points from outputs of an I-axis level discriminating device (1) and a Q-axis level discriminating device (2) to select an optimum path, thus making it possible to reduce a bit error rate (BER).
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公开(公告)号：CA1057367A
公开(公告)日：1979-06-26
申请号：CA260757
申请日：1976-09-08
Applicant: SONY CORP
Inventor： SATO TERUO
Abstract: An FM signal demodulator including a multiplier having a pair of input terminals and an output terminal. A signal coupling circuit is connected between a circuit input terminal and one of the input terminals of the multiplier to couple an FM signal to the multiplier, and a delay line and a phase shifter are connected in cascade between the signal input terminal and the other input terminal of the multiplier. A low pass filter is connected to the output terminal of the multiplier to allow the demodulated signal to reach the circuit output terminal.
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公开(公告)号：CA1056465A
公开(公告)日：1979-06-12
申请号：CA241715
申请日：1975-12-15
Applicant: SONY CORP
Inventor： SATO TERUO , NAKAMURA HIDEO
Abstract: Stereophonic demodulator system for demodulating a stereophonic composite signal that includes a subcarrier frequency of at least 38 KHz, the apparatus including: a circuit for producing a 38 KHz switching signal, a circuit for producing a 114 KHz switching signal, a circuit to which the stereophonic composite signal and the 38 KHz switching signal are supplied to obtain a first demodulated signal, a circuit to which the stereophonic composite signal and the 114 KHz switching signal are supplied to obtain a second demodulated signal, and a circuit for mixing the first and second demodulated signals to produce the desired stereophonic signal free of any accompanying useless signal.
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公开(公告)号：DE2556056A1
公开(公告)日：1976-07-01
申请号：DE2556056
申请日：1975-12-12
Applicant: SONY CORP
Inventor： SATO TERUO , NAKAMURA HIDEO
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