公开(公告)号：JPS6479996A

公开(公告)日：1989-03-24

申请号：JP23705687

申请日：1987-09-21

Applicant: SONY CORP

Inventor： TORII KOICHI

IPC: G11C17/00 ,  G11C16/02

Abstract: PURPOSE:To prevent a soft light from generative by necessarily controlling the control electrode of a memory cell array not to write and the controlled electrode of a memory transistor at the time of writing. CONSTITUTION:Word wires W1, W2... are provided over plural such as two sets of memory cell arrays 1A and 1B, in which a double insulation type FET is made into the memory transistor. At the time of the writing into the array 1A, etc., the control electrode output form a control terminal 14 through an inverter 15 becomes an L, and it does not output a high voltage from a high voltage supplying circuit 11B for the writing of the array 1B not to write. Consequently, the high voltage is not supplied through FET 10B1, 10B2... whose bases are connected with selected word wires W1, W2..., to the bases of controlled electrodes of memory cells FET 3B1-1-3B1-8, 3B2-1-3B2-8.... At the same time, FET 13B1, 13B2... are turned off, and bit wires 13B1, 13B2... to be connected with the drains of the controlled electrodes of the FET 3B1-1-3B1-8, 3B2-1-3B2-8... are made into a floating condition, a current does not flow, and the soft light can be prevented from being generated.

公开(公告)号：JPH0440028A

公开(公告)日：1992-02-10

申请号：JP14702990

申请日：1990-06-05

Applicant: SONY CORP

Inventor： TORII KOICHI ,  OSADA YASUO ,  HOSHINO TAKANARI

IPC: H04K1/00 ,  H04N7/173

Abstract: PURPOSE:To increase the number of channels for scramble signals by connecting plural descramblers in common, identifying the scramble signals and inducing signal outputs only when the descramble operation is enabled. CONSTITUTION:An input part 21 is provided to receive the plural various scramble signals to be transmitted by the same transmission line, and plural descramblers 201A1, 201A2, 201B and 201C to be connected to this input part 21 in common are provided and to respectively scramble the plural scramble signals while being correspondent to those signals, and an output part 23 connected to the plural descramblers in common, and identifying and switching circuits 202A1, 202A2, 202B and 202C are provided to induce the output to the output part 23 in the case of enabling the descramble operations and to inhibit the signal output in the case of disabling the operations. Therefore, the scramble signals are identified and only when the descramble operations are enabled, the signal outputs are induced. Thus, the number of channels for the scramble signals can be increased.

公开(公告)号：JPS6285669A

公开(公告)日：1987-04-20

申请号：JP22403885

申请日：1985-10-08

Applicant: SONY CORP

Inventor： MOCHIZUKI HIDENOBU ,  TORII KOICHI

IPC: H02M3/07 ,  H01L21/8234 ,  H01L27/06

Abstract: PURPOSE:To prevent the lowering of boosted voltage by threshold voltage, to obtain a high voltage drop and to decrease the number of steps for a circuit by using a depletion type element as a high voltage section for the circuit. CONSTITUTION:Diodes D consisting of FETs are cascade-connected in a multistaged manner, and sections among respective step for the diodes D are each connected to first and second clock terminals 1a, 1b at alternate section through capacitors C. A first step in the cascade connection of the diodes D is supplied with supply voltage VDD, clock signals of two phase are fed to the first and second clock terminals 1a, 1b, and boosted voltage is acquired from a final step in the cascade connection of the diodes D. A fixed number of steps on the first step side of the FETs constituting the diodes D are composed of enhancement type elements De, and residual steps on the final step side are organized by depletion type elements Dd.