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公开(公告)号：DE69417823D1
公开(公告)日：1999-05-20
申请号：DE69417823
申请日：1994-08-23
Applicant: SONY CORP
Inventor： UEDA MAMORU
IPC: H04L5/22 , H04J3/00 , H04N7/08 , H04N7/081 , H04N7/52 , H04N7/56 , H04N21/2368 , H04N21/242 , H04N21/43 , H04N21/434 , H04N7/24
Abstract: A method and an apparatus capable of transmitting and receiving multiplexed signals as serial data in such a manner that, even in a state where a continuous signal such as an audio digital signal is not in synchronism with another signal such as a video digital signal, the continuous signal can be properly reproduced on a reception side (20). Address data based on a word clock of another digital signal is sampled (16) on a transmission side in accordance with a sampling clock of the continuous signal, and the sampled address value is included (13) in the multiplexed signals to be thereby transmitted together to the reception side (20). Then on the reception side (20), a word clock synchronously locked to the word clock of the transmission-side another digital signal is reproduced (22) from the received serial data, and address data is generated (23) on the basis of the reproduced word clock, so that the reception-side clock of the continuous signal is reproduced (26) from the generated address data and the transmitted address value included in the multiplexed signals, whereby the continuous signal is reproduced (25) in accordance with the clock thus reproduced.
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公开(公告)号：CA1311834C
公开(公告)日：1992-12-22
申请号：CA573243
申请日：1988-07-28
Applicant: SONY CORP
Inventor： WILKINSON JAMES H , UEDA MAMORU
Abstract: In a system in which a digital video signal is transmitted with differential pulse code modulation, a predetermined number of samples of the digital video signal are grouped, and the center sample of the grouped samples of the digital video signal is transmitted with the original number of bits, while the other samples adjacent to the center sample are differentially modulated with reference to the center sample and are transmitted with the center sample as cluster of samples.
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公开(公告)号：DE69428722D1
公开(公告)日：2001-11-22
申请号：DE69428722
申请日：1994-03-29
Applicant: SONY CORP
Inventor： UEDA MAMORU
Abstract: In a signal processing apparatus having a plurality of signal processing circuits where predetermined data is to be output sequentially through the plurality of signal processing circuits, when signal processing is performed at each signal processing circuit, timing necessary for respective signal processing is added to the data to be transmitted, as a header information, so that a complicated construction, such as a circuit for obtaining timing necessary for signal processing at each signal processing circuit, can be avoided, and the data can be securely processed and delivered at each signal processing circuit.
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公开(公告)号：DE69323506T2
公开(公告)日：1999-09-02
申请号：DE69323506
申请日：1993-03-31
Applicant: SONY CORP
Inventor： UEDA MAMORU
Abstract: When a video signal is recorded on a magnetic tape (14), a high frequency signal component of data converted by a DCT (discrete cosine transform) converter 3 in a DCT fashion or an outer code is recorded on a recording track at its beginning portion in which a waveform of a reproduced output is considerably deteriorated in amplitude when a reproducing head (15) starts to reproduce the recording track. Also, a low frequency signal component of data converted by the DCT converter (3) in a DCT fashion is recorded on the recording track at its succeeding portion in which the reproducing head (15) can stably reproduce the recording track by a recording head (13). The high frequency signal component or outer code is recorded on the area corresponding to the track at its beginning portion in which a waveform of a reproduced output is considerably deteriorated in amplitude when the reproducing head starts to reproduce the same upon playback and the low frequency signal component of data is recorded on the track at its succeeding portion in which the tracing of the reproducing head is stabilized relatively so that, even if a reproducing error occurs and increases because a waveform of a reproduced output is deteriorated in amplitude when the reproducing head starts to trace the recording track, then an amount that a picture quality of a reproduced signal is deteriorated by such error can be reduced considerably.
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公开(公告)号：DE3825917A1
公开(公告)日：1989-02-09
申请号：DE3825917
申请日：1988-07-29
Applicant: SONY CORP
Inventor： WILKINSON JAMES H , UEDA MAMORU
Abstract: In a system in which a digital video signal is transmitted with differential pulse code modulation, a predetermined number of samples alternate in a horizontal line of the digital video signal are grouped, and the center sample of the grouped samples of the digital video signal is transmitted with the original number of bits, while the other samples of a group are differentially modulated with reference to the respective center sample and are transmitted with the center sample as a cluster of samples.
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Patent Agency Ranking
公开(公告)号：EP1187489A4
公开(公告)日：2005-12-14
申请号：EP01921837
申请日：2001-04-13
Applicant: SONY CORP
Inventor： UEDA MAMORU , KANESAKA KOKI , OHARA TAKUMI , YAMAMOTO TAKESHI , MIZUNO KAZUHIRO , MORITA TOSHIKAZU
IPC: H04N5/92 , H03M7/36 , H04N5/76 , H04N7/46 , H04N7/50 , H04N11/04 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/46 , H04N19/50 , H04N19/503 , H04N19/51 , H04N19/587 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/85 , H04N7/24
CPC classification number: H04N19/00 , H04N19/436 , H04N19/577 , H04N19/61 , H04N19/70
Abstract: Upon receiving the parameters of a picture layer, a slice decoder control circuit (46) supplies the parameters of the picture layer and the write pointer of a slice (1) to a slice decoder (47), the parameters of the picture layer and the write pointer of a slice (2) to a slice decoder (48), and the parameters of the picture layer and the write pointer of a slice (3) to a slice decoder (49) sequentially and allow them to be decoded. Based on an input of a signal indicative of completion of decoding from the slice decoders (47) through (49), the slice decoder control circuit (46) commands the slice decoder (48) to perform decoding by supplying the write pointer of a slice (4) at timing A, commands the slice decoder (49) to perform decoding by supplying the write pointer of a slice (5) at timing B, and repeats the similar processing until decoding of the last slice is ended, thus controlling the operation of a plurality of slice decoders.
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公开(公告)号：DE60123168D1
公开(公告)日：2006-11-02
申请号：DE60123168
申请日：2001-05-29
Applicant: SONY CORP
Inventor： UEDA MAMORU
Abstract: A video decoder reproduces an MP ML/MPEG-2 video bit stream at an arbitrary speed using a plurality of slice decoders. When a slice decoder control circuit receives parameters, the slice decoder control circuit sequentially supplies parameters of a picture layer and a write pointer associated with a first slice to a first slice decoder, the parameters of the picture layer and a write pointer associated with a second slice to a second slice decoder, the parameters of the picture layer and a write pointer associated with a third slice to a third slice decoder, so that the slices are decoded by the respective slice decoders. On the basis of signals indicating completion of decoding, received from the first to third slice decoders, the slice decoder control circuit gives commands the first to third slice decoders to decode particular slices.
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公开(公告)号：DE69427244T2
公开(公告)日：2002-06-13
申请号：DE69427244
申请日：1994-03-31
Applicant: SONY CORP
Inventor： UEDA MAMORU
Abstract: In a recording and reproducing apparatus for inputting recording data into a predetermined recording and reproducing means, outputting as reproducing data, when record assurance is conducted by comparing the recording data with the reproduced data, an error detection code is calculated for the recording data, and the error detection code is compared with the error detection code which is obtained from the reproduced data by a predetermined comparison means, thereby allowing the volume of information to be transmitted from the recording system to the comparison means to be considerably reduced. Therefore, the capacity of the delay memory for delaying the error detection code which is calculated from the recording data for the portion of the processing time in the recording and reproducing means can be considerably reduced.
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公开(公告)号：DE69416372D1
公开(公告)日：1999-03-18
申请号：DE69416372
申请日：1994-03-29
Applicant: SONY CORP
Inventor： UEDA MAMORU
Abstract: In a signal processing apparatus having a plurality of signal processing circuits where predetermined data is to be output sequentially through the plurality of signal processing circuits, when signal processing is performed at each signal processing circuit, timing necessary for respective signal processing is added to the data to be transmitted, as a header information, so that a complicated construction, such as a circuit for obtaining timing necessary for signal processing at each signal processing circuit, can be avoided, and the data can be securely processed and delivered at each signal processing circuit.
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公开(公告)号：AU2006688A
公开(公告)日：1989-02-02
申请号：AU2006688
申请日：1988-07-27
Applicant: SONY CORP
Inventor： WILKINSON JAMES H , UEDA MAMORU
Abstract: In a system in which a digital video signal is transmitted with differential pulse code modulation, a predetermined number of samples alternate in a horizontal line of the digital video signal are grouped, and the center sample of the grouped samples of the digital video signal is transmitted with the original number of bits, while the other samples of a group are differentially modulated with reference to the respective center sample and are transmitted with the center sample as a cluster of samples.
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