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    TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD
    1.
    发明申请
    TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD 审中-公开

    公开(公告)号：WO2018092614A1

    公开(公告)日：2018-05-24

    申请号：PCT/JP2017039856

    申请日：2017-11-06

    Applicant: SONY CORP

    Inventor： SHINOHARA YUJI ,  YAMAMOTO MAKIKO

    IPC: H03M13/19

    Abstract: The present invention relates to a transmission device, a transmission method, a reception device, and a reception method, whereby good communications quality can be ensured during data transmission using LDPC codes. LDPC encoding is performed on the basis of check matrices for LDPC codes having a code length N of 69,120 bits and an encoding rate r of 5/16, 6/16, 7/16, or 8/16. The check matrices include: an A matrix of M1 rows and K columns, indicated by a prescribed value M1 and LDPC code information length K = N×r; a B matrix having a staircase structure of M1 rows and M1 columns; a Z matrix being a zero matrix having M1 rows and N–K–M1 columns; a C matrix having N–K–M1 rows and K+M1 columns; and a D matrix being a unit matrix of N–K–M1 rows and N–K–M1 columns. The A matrix and C matrix are indicated by a check matrix initial value table. The check matrix initial value table indicates the position of one element in the A matrix and the C matrix, for every 360 columns, and is a predetermined table. The present invention is applicable, e.g., to data transmission, etc., using LDPC codes.

    ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY
    2.
    发明申请
    ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY 审中-公开
    提供增量冗余的编码器和编码方法

    公开(公告)号：WO2011104182A3

    公开(公告)日：2011-11-17

    申请号：PCT/EP2011052417

    申请日：2011-02-18

    Applicant: SONY CORP ,  SONY DEUTSCHLAND GMBH ,  MUHAMMAD NABIL ,  STADELMEIER LOTHAR ,  ROBERT JOERG ,  ATUNGSIRI SAMUEL ASANGBENG ,  YAMAMOTO MAKIKO ,  SHINOHARA YUJI ,  SAKAI LUI ,  YOKOKAWA TAKASHI

    Inventor： MUHAMMAD NABIL ,  STADELMEIER LOTHAR ,  ROBERT JOERG ,  ATUNGSIRI SAMUEL ASANGBENG ,  YAMAMOTO MAKIKO ,  SHINOHARA YUJI ,  SAKAI LUI ,  YOKOKAWA TAKASHI

    IPC: H03M13/11 ,  H04L1/00

    CPC classification number: H03M13/11 ,  H03M13/1165 ,  H03M13/3761 ,  H03M13/6519 ,  H04L1/0036 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0059 ,  H04L1/0068 ,  H04L1/0083 ,  H04L2001/0098

    Abstract: The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number K ldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number N ldpc - K ldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number M IR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address ?, wherein said parity symbol addresses ? are determined according to a second address generation rule N ldpc - K ldpc + {x + m mod G a x Q IR } mod M IR if x > N ldpc - K ldpc ' wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and Q IR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).

    Abstract translation: 本发明涉及一种用于将输入数据字（D）编码为码字（Z1，Z2）的编码器，包括：编码器输入（1451），用于接收输入数据字（D），每个输入数据字包括第一数目K ldpc 信息符号;编码装置（1452），用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4），使得码字包括包含数据部分（D）的基本码字部分（B）;以及 基本奇偶校验码元的第二数量N ldpc -K ldpc的基本奇偶校验部分（Pb）以及包括辅助奇偶校验码元的第三数目M IR的辅助奇偶部分（Pa）的辅助码字部分（A），其中所述 编码装置（14）适于：i）根据第一码从输入数据字（D）产生所述基本码字部分（B），其中通过在确定的奇偶校验符号地址处累积信息符号来产生基本奇偶校验符号 根据第一个地址生成规则，以及ii）用于生成 根据第二代码从输入数据字（D）中除去所述辅助码字部分（A），其中辅助奇偶校验符号通过在奇偶校验符号地址β处累积信息符号m而产生， 根据第二地址生成规则N ldpc -K ldpc + {x + m mod G ax Q IR} mod M IR确定，如果x> N ldpc -K ldpc'，其中x表示与所述第一地址生成规则相对应的奇偶符号累加器的地址 尺寸Ga和Q IR组的第一个信息符号是一个辅助码率相关的预定义常数，和一个用于输出所述码字（Z1，Z2）的编码器输出（1454）。

    RECEPTION DEVICE AND RECEPTION METHOD
    3.
    发明公开
    RECEPTION DEVICE AND RECEPTION METHOD 审中-公开

    公开(公告)号：EP3197174A4

    公开(公告)日：2018-05-23

    申请号：EP15835423

    申请日：2015-08-14

    Applicant: SONY CORP

    Inventor： YOSHIMOCHI NAOKI ,  YOKOKAWA TAKASHI ,  MATSUMOTO HIDEYUKI ,  OKADA SATOSHI ,  YAMAMOTO MAKIKO

    IPC: H04N21/4425 ,  H04H60/37 ,  H04J3/00 ,  H04L1/00 ,  H04N21/434

    CPC classification number: H04H60/11

    Abstract: The present technology relates to a reception apparatus for enabling the influence of an error during transmission to be minimized in channel bonding, and a reception method. The reception apparatus receives a plurality of divided streams acquired by distributing BB frames of a BB stream which is a stream of BB frames to a plurality of data slices, when an error occurs during transmission and time information on an order of selection of the BB frames when the plurality of the divided streams are reconstructed cannot be acquired, estimates the BB frame to be selected next from among the selectable BB frames for each of the plurality of the divided streams on the basis of information on the BB frames, and selects the next BB frame from among the selectable BB frames on the basis of an estimation result of the BB frame. The present technology is applicable to channel bonding such as PLP bundling.

    DATA PROCESSING DEVICE, AND DATA PROCESSING METHOD
    7.
    发明公开
    DATA PROCESSING DEVICE, AND DATA PROCESSING METHOD 有权
    DATENVERARBEITUNGSVORRICHTUNG UND DATENVERARBEITUNGSVERFAHREN

    公开(公告)号：EP2879298A4

    公开(公告)日：2016-04-13

    申请号：EP14810530

    申请日：2014-06-03

    Applicant: SONY CORP

    Inventor： SHINOHARA YUJI ,  YAMAMOTO MAKIKO

    IPC: H03M13/11 ,  H03M13/03 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/35 ,  H04L1/00

    CPC classification number: H03M13/118 ,  H03M13/036 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2906 ,  H03M13/356 ,  H03M13/616 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071

    Abstract: The present technology relates to a data processing apparatus and a data processing method that are able to provide an LDPC code with a good error rate. An LDPC encoder performs coding by an LDPC code having a code length of 16200 bits and a code rate of 12/15. The LDPC code includes an information bit and a parity bit, and a parity check matrix H is configured with an information matrix portion corresponding to the information bit of the LDPC code and a parity matrix portion corresponding to the parity bit. An information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table representing a position of an element of 1 in the information matrix portion at an interval of 360 columns. The present technology may be applied to a case of performing an LDPC coding and an LDPC decoding.

    Abstract translation: 本技术涉及能够提供具有良好错误率的LDPC码的数据处理装置和数据处理方法。 LDPC编码器通过具有16200比特的码长和12/15的码率的LDPC码执行编码。 LDPC码包括信息位和奇偶位，奇偶校验矩阵H配置有与LDPC码的信息比特对应的信息矩阵部分和对应于奇偶校验位的奇偶校验矩阵部分。 奇偶校验矩阵H的信息矩阵部分由以360列的间隔表示信息矩阵部分中元素1的位置的奇偶校验矩阵初始值表表示。 本技术可以应用于执行LDPC编码和LDPC解码的情况。

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