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公开(公告)号：AT87156T
公开(公告)日：1993-04-15
申请号：AT87300607
申请日：1987-01-23
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI , YAMAGAMI TAMOTSUO
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公开(公告)号：AT87155T
公开(公告)日：1993-04-15
申请号：AT87300187
申请日：1987-01-09
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI
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公开(公告)号：GB2106759A
公开(公告)日：1983-04-13
申请号：GB8226039
申请日：1982-09-13
Applicant: SONY CORP
Inventor： YAMAMURA SHINICHI
Abstract: A circuit for detecting existence of an information signal comprising an input circuit provided for supply with the information signal, a clamp circuit for clamping a signal obtained from the input circuit to a predetermined fixed DC level, a level detector for detecting the amplitude level of an output of the clamp circuit and for producing a DC output with its level corresponding to the detected amplitude level, and a level comparator for comparing the DC output from the level detector with a predetermined reference voltage to produce an output signal assuming a first level when the DC output is higher than the reference voltage and a second level when the DC output is lower than the reference voltage. The first level or second level of the output signal from the level comparator indicates that the information signal is supplied to the input circuit.
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公开(公告)号：AU604836B2
公开(公告)日：1991-01-03
申请号：AU1146888
申请日：1988-02-09
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI
Abstract: An error-correcting method and apparatus for a block of data (D0 to D511) provided with an error-correcting parity (C1, C2) for error correction and an error-checking parity (EDC) that can be used to generate a syndrome for error-checking, in which error correction is carried out by the use of the error-correcting parity (C1, C2) and then an error check is carried out by the use of the error-checking parity (EDC) thereby to increase the reliability of the error-corrected data. Error information produced by the error-correction process using the error-correcting parity (C1, C2) is utilised to correct the syndrome used in the error-checking process, so as to execute the respective operations in parallel and reduce the required data processing or through-put time.
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公开(公告)号：AU601388B2
公开(公告)日：1990-09-13
申请号：AU6716487
申请日：1987-01-06
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI
Abstract: A product code arranged in a rectangular array is formed of a data portion comprising data bytes (D0 to D523), an error detecting code (EDC), and parity portions (C1 and C2). A generator for the product code includes a RAM for storing the data and parity codes. The error detecting code (EDC) is generated at the same time as the parity code, thereby reducing the processing time. The error detecting code (EDC) is processed with the data to produce the parity code of the corresponding data block. A decoder for the code corrects errors on the basis of the parity codes but, upon receipt of a data request signal, error correction is interrupted and the required data is output as long as no error is detected on the basis of the error detecting code (EDC).
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Patent Agency Ranking
公开(公告)号：AU5604286A
公开(公告)日：1986-10-16
申请号：AU5604286
申请日：1986-04-11
Applicant: SONY CORP
Inventor： SAKO YOIICHIRO , YAMAMURA SHINICHI , ARAI MASAYUKI
Abstract: A method of correcting errors in digital data comprising a data block made up of a predetermined number of symbols, in which a first and a second series of error corrector codes have been added to the data, the method comprising performing an error correcting process consisting of repeatedly correcting the data using the first and second code series, detecting the occurrence of a data request signal requesting the data, and terminating execution of the error correcting process in response to receipt of the data request signal.
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公开(公告)号：CA1191559A
公开(公告)日：1985-08-06
申请号：CA410982
申请日：1982-09-08
Applicant: SONY CORP
Inventor： YAMAMURA SHINICHI
Abstract: CIRCUITS FOR DETECTING EXISTENCE OF AN IMFORMATION SIGNAL A circuit for detecting existence of an information signal comprising input circuit means provided to be supplied with the information singal, clamp circuit means for clamping a signal obtained from the input circuit means to a predetermined fixed DC level, a level detector for detecting the amplitude level of an output of the clamp circuit means and producing a DC output with its level corresponding to the detected amplitude level, and a level comparator for comparing the DC output from the level detector with a predetermined reference voltage to produce an output signal taking a fist level when the DC output is higher than the reference voltage and a second level when the DC output is lower than the reference voltage. The first level or second level of the output signal from the level comparator indicates that the information signal is supplied to the input circuit means.
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公开(公告)号：DE3233893A1
公开(公告)日：1983-03-31
申请号：DE3233893
申请日：1982-09-13
Applicant: SONY CORP
Inventor： YAMAMURA SHINICHI
Abstract: A circuit for detecting existence of an information signal comprising an input circuit provided for supply with the information signal, a clamp circuit for clamping a signal obtained from the input circuit to a predetermined fixed DC level, a level detector for detecting the amplitude level of an output of the clamp circuit and for producing a DC output with its level corresponding to the detected amplitude level, and a level comparator for comparing the DC output from the level detector with a predetermined reference voltage to produce an output signal assuming a first level when the DC output is higher than the reference voltage and a second level when the DC output is lower than the reference voltage. The first level or second level of the output signal from the level comparator indicates that the information signal is supplied to the input circuit.
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公开(公告)号：SG19395G
公开(公告)日：1995-08-18
申请号：SG19395
申请日：1995-02-04
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI , ARAI MASAYUKI
Abstract: A method of correcting errors in digital data comprising a data block made up of a predetermined number of symbols, in which a first and a second series of error corrector codes have been added to the data, the method comprising performing an error correcting process consisting of repeatedly correcting the data using the first and second code series, detecting the occurrence of a data request signal requesting the data, and terminating execution of the error correcting process in response to receipt of the data request signal.
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公开(公告)号：AU594995B2
公开(公告)日：1990-03-22
申请号：AU6785687
申请日：1987-01-21
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI , YAMAGAMI TAMOTSU
Abstract: A data transmission method in which a rectangular array is formed of a block of data containing n words, supplementary data (SUPD) necessary to transmit the n words of data and an error detecting code (EDC) to detect possible errors which may occur in the block of data and in the supplementary data (SUPD). An error correcting code (C₁,C₂) is produced for each row and column of data of the rectangular array and added thereto thereby to form product-coded data, each data word of which is thereafter sequentially fetched and transmitted along each row of the product-coded data. When the block of data is changed from n data words to m data words, the number of data words in one direction of the rectangular array is fixed, while the number of data words in the other direction of the rectangular array is changed, thereby to form a new rectangular array which is also sequentially fetched and transmitted along each row of the array. A similar method can be used for recording data on a recording medium.
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