公开(公告)号：EP2270990A3

公开(公告)日：2011-06-22

申请号：EP10178046.8

申请日：2004-04-19

Applicant: Sony Corporation

Inventor： Yokokawa, Takashi ,  Miyauchi, Toshiyuki ,  Iida, Yasuhiro

IPC: H03M13/11

CPC classification number: H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

Abstract: The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculation.

公开(公告)号：EP1940174B1

公开(公告)日：2011-09-28

申请号：EP07150132.4

申请日：2007-12-19

Applicant: Sony Corporation

Inventor： Iida, Yasuhiro

IPC: H04N7/24 ,  H04N5/00

CPC classification number: H04N21/23406 ,  H04N21/2365 ,  H04N21/4305 ,  H04N21/434 ,  H04N21/4347 ,  H04N21/44004

Abstract: An information processing apparatus that processes a multiplexed stream including a frame having multiple slots, which is obtained by multiplexing multiple streams (FEC OUTPUT DATA) containing time information describing times is disclosed. The apparatus includes extracting means (61) for extracting predetermined one or more slots from the frame of the multiplexed stream, storage means (63) for storing data of the slot(s), and frequency dividing means (62) for generating a second clock signal by frequency-dividing a first clock signal by a frequency division ratio N:M based on the number of clocks N corresponding to the time for one frame in the multiplexed stream and the number of clocks M for reading the data of the slot(s) extracted from the one frame from the storage means (63) in the time for the one frame. The data of the slot or slots stored in the storage means (63) is read in synchronization with the second clock signal.

公开(公告)号：EP2270989A3

公开(公告)日：2011-06-22

申请号：EP10178005.4

申请日：2004-04-19

Applicant: Sony Corporation

Inventor： Yokokawa, Takashi ,  Miyauchi, Toshiyuki ,  Iida, Yasuhiro

IPC: H03M13/11

CPC classification number: H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

Abstract: The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

Abstract translation: 本发明涉及用于实现LDPC码的解码的解码装置和解码方法，其中，在抑制电路规模的同时，可以将操作频率抑制在足够可行的范围内，并且可以执行对存储器访问的控制 很容易，并为此编程。 LDPC码的校验矩阵由（P×P）单位矩阵，单位矩阵的1到几个1被替换为0的矩阵，它们被循环移位的矩阵，矩阵， 这是它们中的两个或更多个的总和，以及（P×P）0矩阵。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p个变量节点计算。

公开(公告)号：EP0360517B1

公开(公告)日：1994-11-09

申请号：EP89309429.2

申请日：1989-09-18

Applicant: SONY CORPORATION

Inventor： Miura, Masayoshi ,  Inagawa, Kiyofumi ,  Sogawa, Hiroyuki ,  Iida, Yasuhiro

IPC: H04R1/10

CPC classification number: H04R1/2857 ,  G10K11/22 ,  H04R1/1016 ,  H04R1/1075 ,  H04R1/288 ,  H04R1/345

公开(公告)号：EP2270989A2

公开(公告)日：2011-01-05

申请号：EP10178005.4

申请日：2004-04-19

Applicant: Sony Corporation

Inventor： Yokokawa, Takashi ,  Miyauchi, Toshiyuki ,  Iida, Yasuhiro

IPC: H03M13/11

CPC classification number: H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

Abstract: The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

Abstract translation: 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器存取的控制 很容易，也是一个程序。 LDPC码的校验矩阵由（P×P）个单位矩阵，单位矩阵中的1至数个1被0替代的矩阵，循环移位的矩阵，矩阵， 它们是两个或更多个的和，（P×P）0矩阵的和。 校验节点计算器313同时执行p校验节点计算。 可变节点计算器319同时执行p个可变节点计算。

公开(公告)号：EP0113980B1

公开(公告)日：1987-07-22

申请号：EP83307648.2

申请日：1983-12-15

Applicant: SONY CORPORATION

Inventor： Imakoshi, Shigeyoshi ,  Souda, Yutaka ,  Suyama, Hideo ,  Iida, Yasuhiro

IPC: G11B5/39

CPC classification number: G11B5/3903

公开(公告)号：EP0107982A3

公开(公告)日：1987-01-14

申请号：EP83306602

申请日：1983-10-28

Applicant: SONY CORPORATION

Inventor： Souda, Yutaka ,  Imakoshi, Shigeyoshi ,  Suyama, Hideo ,  Uchida, Hiroyuki ,  Iida, Yasuhiro ,  Sekiya, Tetsuo

IPC: G11B05/39

CPC classification number: G11B5/3903 ,  G11B5/40

Abstract: A magnetic transducer head utilising magnetoresistance effect comprises means for applying a constant voltage (V 1 , V 2 ) to both ends of at least one pair of magnetoresistance effect elements (MR n1 , MR n2 ) connected in series on a discontinuous portion other than a magnetic gap of a magnetic core forming a magnetic gap, and means for applying bias magnetic fields (H B , -H B ) of opposite polarity to the respective magnetoresistance effect elements, an output being derived from a connection point between the pair of magnetoresistance effect elements.

公开(公告)号：EP0107982A2

公开(公告)日：1984-05-09

申请号：EP83306602.0

申请日：1983-10-28

Applicant: SONY CORPORATION

Inventor： Souda, Yutaka ,  Imakoshi, Shigeyoshi ,  Suyama, Hideo ,  Uchida, Hiroyuki ,  Iida, Yasuhiro ,  Sekiya, Tetsuo

IPC: G11B5/39

CPC classification number: G11B5/3903 ,  G11B5/40

Abstract: A magnetic transducer head utilising magnetoresistance effect comprises means for applying a constant voltage (V 1 , V 2 ) to both ends of at least one pair of magnetoresistance effect elements (MR n1 , MR n2 ) connected in series on a discontinuous portion other than a magnetic gap of a magnetic core forming a magnetic gap, and means for applying bias magnetic fields (H B , -H B ) of opposite polarity to the respective magnetoresistance effect elements, an output being derived from a connection point between the pair of magnetoresistance effect elements.

公开(公告)号：EP2101465A3

公开(公告)日：2014-04-09

申请号：EP09250611.2

申请日：2009-03-04

Applicant: Sony Corporation

Inventor： Kawauchi, Hidetoshi ,  Miyauchi, Toshiyuki ,  Yokokawa, Takashi ,  Horiguti, Takashi ,  Yoshimochi, Naoki ,  Iida, Yasuhiro ,  Hori, Satoru

IPC: H04L27/26 ,  H04L25/03

CPC classification number: H04L27/2647 ,  H04L25/0232 ,  H04L25/03821

Abstract: Disclosed herein is a demodulating circuit including: an FFT processing section; a component for removing intercarrier interference; an extracting section; a section for estimating transmission path characteristics; an interpolating section; a section for estimating symbol sequences; and a section for generating interference replicas.

公开(公告)号：EP2270990A2

公开(公告)日：2011-01-05

申请号：EP10178046.8

申请日：2004-04-19

Applicant: Sony Corporation

Inventor： Yokokawa, Takashi ,  Miyauchi, Toshiyuki ,  Iida, Yasuhiro

IPC: H03M13/11

CPC classification number: H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

Abstract: The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculation.

Abstract translation: 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器存取的控制 很容易，也是一个程序。 LDPC码的校验矩阵由（P×P）个单位矩阵，单位矩阵中的1至数个1被0替代的矩阵，循环移位的矩阵，矩阵， 它们是两个或更多个的和，（P×P）0矩阵的和。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。