公开(公告)号：US20230081697A1

公开(公告)日：2023-03-16

申请号：US17992132

申请日：2022-11-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Wei GE ,  Chongyang LI ,  Leidong ZHENG ,  Yifei WANG

IPC: G06F21/60

Abstract: The present disclosure discloses an information security application-oriented reconfigurable system chip compiler and an automatic compilation method. The method includes the following steps: firstly, inputting a source program of a cryptographic algorithm; then, executing a software compilation function syntax check of the source program, and when the check result is passed, performing compilation mapping using a compiler; next, executing the cryptographic algorithm by simulation running using a simulator, and generating a configuration code by a simulator array; and finally, guiding a hardware behavior operation using a binary configuration code file generated by the simulator. The reconfigurable system chip compiler includes a source program input module, a software compilation function verification module, a compilation mapping module, a simulation execution module, a configuration code generation module, and a hardware debugging module.

公开(公告)号：US20200342295A1

公开(公告)日：2020-10-29

申请号：US16757421

申请日：2019-01-24

Applicant: Southeast University

Inventor： Bo LIU ,  Yu GONG ,  Wei GE ,  Jun YANG ,  Longxing SHI

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption. The accumulation calculation circuit is composed of a delay accumulation circuit, a TDC conversion circuit, and a shift-addition circuit in series. The delay accumulation circuit comprises eight controllable delay chains for dynamically controlling the number of iterations and accumulating data multiple times in a time domain, so as to meet the difference in calculation scale of different network layers, save hardware storage space, reduce calculation complexity, and reduce data scheduling.

公开(公告)号：US20240223367A1

公开(公告)日：2024-07-04

申请号：US18349500

申请日：2023-07-10

Applicant: SOUTHEAST UNIVERSITY

Inventor： Wei GE ,  Chongyang LI ,  Mingfeng ZHANG ,  Shuhe LIU ,  Shenian WEI

IPC: H04L9/16

CPC classification number: H04L9/16

Abstract: A loop array mapping method of a shared balance operator is based on a reconfigurable cryptographic algorithm. The mapping graph is optimized by adopting a balance node operator mode, so that the mapping graph has a smallest iteration interval and a largest pipeline performance, thus solving a problem of poor pipeline performance of manual configuration and saving a great deal of human and mental labor, without adding the balance operator node manually by manual computing. In the present disclosure, a shared balance node operator solution is adopted to process a balance node of the multi-fan-out operator, so that computation resources are minimized and performance is maximized. The storage data unit SREG is used for data transfer and communication, which solves a problem that communication of data between loop bodies occupies more transfer operator resources, saves a lot of hardware resources and further improves pipeline performance.

公开(公告)号：US20230359448A1

公开(公告)日：2023-11-09

申请号：US18223724

申请日：2023-07-19

Applicant: SOUTHEAST UNIVERSITY

Inventor： Wei GE ,  Chongyang LI ,  Qingxiao ZHOU ,  Yanhong XU

IPC: G06F8/41

CPC classification number: G06F8/443 ,  G06F8/433

Abstract: The present disclosure provides an interpreter of a reconfigurable cryptographic algorithm based on customized high-level C language, in the field of information security. The interpreter includes an input program of cryptographic algorithm customized language, a compilation optimization module, an intermediate file and data flow graph generation module, a mapping module and an array generation configuration code module. The disclosure provides an automatic mapping tool for the reconfigurable processor, which can take customized high-level C language as input, and the interpreter arranges and connects computing units like operators according to the input high-level C program, to complete the mapping of the whole computing function. This can shorten the development cycle of the reconfigurable system, reduce the hardware mastery requirements for users, map the computing units of different parts to the reconfigurable processor in a more optimized way, and effectively enhance the performance of the reconfigurable processor.