公开(公告)号：JPH10334656A

公开(公告)日：1998-12-18

申请号：JP13359598

申请日：1998-05-15

Applicant: ST MICROELECTRON INC

Inventor： ARTIERE ALAIN

IPC: G11C11/412 ,  G11C11/401 ,  G11C11/402 ,  G11C11/403 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To implement in parallel many refresh operations in single cycle and reduce bandwidth for refresh operation by setting individual memory cell access and memory transistors in such a ratio of the modes to refresh the memory cell information with activation of the related word line. SOLUTION: An individual dynamic memory cell 102 of a dynamic memory cell 100 couples the drains of a pair of cross-connected N-channel MOS transistors 104, 106 to the bit lines 114, 116 via the N-channel access transistors 108, 110 and then connects the gates of transistors 1089, 110 to the word line 112. The refresh operation of memory cell 100 is performed by enabling the gate of transistor 108 and then activating the word line 112. Thereby, the memory cell 102 can be refreshed simultaneously using the multi-word line activating circuit 126.