公开(公告)号：JPH1167971A

公开(公告)日：1999-03-09

申请号：JP14974098

申请日：1998-05-29

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSIU C ,  LAWRENCE P ENG

IPC: H05K1/18 ,  H01L23/12 ,  H01L23/14

Abstract: PROBLEM TO BE SOLVED: To provide a high-level integration for forming the entire system, by forming an interconnection layer on a board and fixing integrated circuits to the interconnection layer. SOLUTION: An integrated circuit package comprises a board 12, and integrated circuits 14, 16, 18, 20, 22 which are fixed to the board 12 and comprise integrated circuit outer connections, contacts or bond pads 24, 26, 28, 30, 23. An Si wafer or board 12 comprises board contacts or bond pads 34, 36, 38, 40, 42. Interconnections or bonding wires 44 are formed between the integrated circuit 24, 26, 28, 30, 32 and bond pads 34, 36, 38, 40, 42 to form electric connections from the integrated circuits 14, 16, 18, 20, 22 to the board 12, thereby expanding the capability for integrating many chips or integrated circuits.