公开(公告)号：JPH10254699A

公开(公告)日：1998-09-25

申请号：JP35647097

申请日：1997-12-25

Applicant: ST MICROELECTRON INC

Inventor： ISAMAN DAVID L

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/318 ,  G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To decrease the number of needed clocks and to facilitate floating point exchanging operation by allowing a physical register to hold the same contents for respective exchange instructions. SOLUTION: An instruction server 106 retrieves one or more insurrections from an instruction cache 104. Four parcels are stored in parcel registers 108A to 108D. Each parcel register sends the parcels to corresponding decoders 110A to 110D, which decode the parcels, determine whether or not the parcels have a floating point exchange instruction, and further determine their operand registers. Then the decoded instructions are sent to corresponding logic units 112A to 112D. The logic units 112A to 112D further receive top-of-stack information and also receive current or existing FXCH maps each time a floating point exchange instruction is received.