公开(公告)号：JPH10240615A

公开(公告)日：1998-09-11

申请号：JP35423697

申请日：1997-12-24

Applicant: ST MICROELECTRON INC

Inventor： LYSINGER MARK A

IPC: G06F12/06 ,  G11C7/10 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To improve operation speed by transferring decoded memory address information from a second decoded address storage circuit to a first decoded address storage circuit. SOLUTION: A memory device 50 has a memory array 52 and the memory array 52 is subdivided into plural memory array blocks 54. The memory circuit has plural data storage positions and addresses related to the respective data storage positions. The first decoded address storage circuit stores the first decoded memory address and holds it for access to the specified memory address. The second decoded address storage circuit stores the second decoded memory address and holds it for access to the second decoded memory address. A control circuit operates in such a way that decoded memory address information is transferred to the first decoded address storage circuit from the second decoded address storage circuit.