SACRIFICIAL SPACER FOR INTEGRATED CIRCUIT TRANSISTOR

    公开(公告)号:JPH1145944A

    公开(公告)日:1999-02-16

    申请号:JP15008798

    申请日:1998-05-29

    Abstract: PROBLEM TO BE SOLVED: To form a self-aligned contact easily by providing a side wall spacer during a process for forming an LDD region and then removing the side wall spacer before a device is processed furthermore. SOLUTION: A polysilicon layer is formed and patterned before being etched to form conductive polysilicon electrodes 90, 92. Side wall spacers 86, 88 isolate gate electrodes 60, 62 from interconnection leads 90, 92. A contact to an underlying substrate 40 is isolated from the electrodes 60, 62 only by the thickness of the spacers 86, 88. Consequently, the contact can be brought close to the gate electrodes 60, 62 using a sacrificial layer for the LDD side wall spacer. Since a larger contact region is provided, the contact resistance is decreased or the inter-element interval is shortened resulting in the overall dimensional reduction of the device.

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