公开(公告)号：SG145620A1

公开(公告)日：2008-09-29

申请号：SG2008008302

申请日：2008-01-30

Applicant: ST MICROELECTRONICS ASIA

Inventor： GUEDON YANNICK ,  DARMAWAN YOSEPH ADHI

Abstract: Output Architecture for LCD Panel Column Driver In one embodiment consistent with the present invention, a digital to analog converter (DAC) circuit operates over an upper range and a lower range. An upper voltage node is designated AVDD; a middle voltage node is designated HVDD; and a lower voltage node designated ground. An upper DAC stage has at least one NMOS transistors that produces an output to an upper range output node when the output is in the upper range. A lower DAC stage has at least one PMOS transistors that produces an output to a lower range output node when the output is in the lower range. A body bias control circuit couples the body of the upper NMOS transistor to a voltage source equal to HVDD-Vbe and connects the body of the lower PMOS transistor to voltage source equal to HVDD+Vbe. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.