公开(公告)号：JPH11242895A

公开(公告)日：1999-09-07

申请号：JP32394698

申请日：1998-11-13

Applicant: ST MICROELECTRONICS INC

Inventor： ARTIERI ALAIN

IPC: G11C17/18 ,  G11C7/00 ,  G11C17/12

Abstract: PROBLEM TO BE SOLVED: To save power and also to attain the quick access by reorganize a memory so that the number of 1s of memory cells of respective rows and columns of an array become smaller than that of 0s of the cells to reduce the number of transistors to be connected to bit lines. SOLUTION: When the number of 1s in respective rows and respective columns of data cells of a matrix shaped array is larger than the number of 0s, the reorganizing of the memory is performed by inverting the data cells alternately every row and column and by performing inversions repeatedly until all rows and columns become so as to have at least the number of 1s equal to that of the number of 0s. Then, flag data at that time are stored in corresponding flag memories being in the cells to be connected to inverters 122. Transistors of only, memory cells having 1s are connected to bit lines 116. As a result, the number of running transistors is reduced by reorganizing a memory 100 while reducing the number of cells having is in this manner. Moreover, a data circuit array has cells for storages 110 of the reorganized array, a data read circuit and an address circuit and the inverting of bits are performed by XOR gates 120.