公开(公告)号：JP2003264454A

公开(公告)日：2003-09-19

申请号：JP2002372307

申请日：2002-12-24

Applicant: ST MICROELECTRONICS INC

Inventor： CHOW JAMES ,  LAY KHIN ,  WEN KENNY D

IPC: H03K17/00 ,  G11C11/409 ,  G11C27/02 ,  H03F3/45 ,  H03K3/356 ,  H03K17/687 ,  H04L25/02

Abstract: PROBLEM TO BE SOLVED: To provide an electric signal sampling circuit with enhanced accuracy. SOLUTION: A differential data sampling circuit is provided for sampling an input signal line with precise timing so as to provide reduced sensitivity to noise. The differential data sampling circuit includes a latch circuit for initially sampling a differential data signal in response to a first strobe signal. The latch circuit operates to rapidly capture the signal level present on the input signal line. The output of the latch circuit is sampled by a strobe circuit in order to sample and hold the output of the latch circuit based on a second strobe signal. In preferred embodiments, the latch circuit has a high input impedance. A digital data receiver including such a differential data sampling circuit is also provided. COPYRIGHT: (C)2003,JPO

公开(公告)号：DE60204631D1

公开(公告)日：2005-07-21

申请号：DE60204631

申请日：2002-05-28

Applicant: ST MICROELECTRONICS INC

Inventor： CHOW JAMES ,  WEN KENNY

IPC: H03H7/30 ,  H03L7/07 ,  H03L7/081 ,  H03L7/10

Abstract: A closed loop delay line system (700) includes a phase lock loop that provides a phase lock output signal (715). A delay line (702) includes a clock input, a delay line output, and a delay line bias input. A bias signal provided to the delay line bias input (727) adjusts the speed of the delay line (702). A phase detector (720) compares phase between a first timing signal input (704) and the delay line output (706). A bias adjust circuit (726) mixes the phase compare output signal (725) and the phase lock output signal (715) to provide a combination bias signal (727) to the delay line (702). Additionally, the relative timing position of strobe outputs (734) from the delay line (702) can be individually adjusted.