公开(公告)号：JP2003208304A

公开(公告)日：2003-07-25

申请号：JP2002377352

申请日：2002-12-26

Applicant: ST MICROELECTRONICS INC

Inventor： CHREN WILLIAM A JR

IPC: G06F7/00 ,  G06F7/72 ,  H03M7/18

Abstract: PROBLEM TO BE SOLVED: To provide an improved arithmetic circuit to be used with a residue number system (RNS). SOLUTION: A self-synchronized data processing circuit module is provided. Data are provided to the data processing circuit along with a request handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is an OHRNS (one hot residue number system) arithmetic processing circuit. The data processing circuit processes the input data while the request input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the request signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a 'data ready' output. COPYRIGHT: (C)2003,JPO