公开(公告)号：JP2000151713A

公开(公告)日：2000-05-30

申请号：JP27804499

申请日：1999-09-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHRISTIAN D CASPER

IPC: G06F13/00 ,  H04L12/56 ,  H04L13/08 ,  H04L29/06 ,  H04L12/44

Abstract: PROBLEM TO BE SOLVED: To provide an improved method and a system which perform routing of data adjusted to a frame based on a network. SOLUTION: A host processor 44 starts an address lookup algorithm for analyzing burst of transferred data and feeding a frame to a desired destination. A common system memory 46 receives data including an address field selected in advance. A network device has plural ports and each port has a FIFO reception memory for receiving at least a first part of the frame. This first part has data equipped with the address field selected beforehand. A DMA unit transfers burst of the data from the FIFO reception memory to the common system memory 46. A communication processor selects an amount of data to be transferred from the FIFO reception memory on the basis of the desired address field to be analyzed by the host processor.

公开(公告)号：JP2000200241A

公开(公告)日：2000-07-18

申请号：JP27916899

申请日：1999-09-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHRISTIAN D CASPER

IPC: G06F13/12 ,  G06F5/06 ,  G06F13/00 ,  G06F13/38 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To constitute a data structure by using a descriptor link in a network device by constructing a descriptor which points a frame data buffer in a common memory and storing the descriptor. SOLUTION: Four network controllers 40 are connected to a 32-bit system bus connected to a host system 43. A host microprocessor 44 is connected to the system bus 42 as well as a common memory subsystem 46. In this case, the network device itself serves to constitute a buffer structure for, e.g. the frame data buffer, a relative descriptor link, and a descriptor. The network device constructs a transmission and/or reception descriptor link in a memory used externally in common to the host system. The network device constructs one ore more descriptors, each of which points the frame data buffer in the common memory. Then, the descriptors are stored.

公开(公告)号：JP2000194655A

公开(公告)日：2000-07-14

申请号：JP27788199

申请日：1999-09-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHRISTIAN D CASPER

IPC: G06F13/38 ,  G06F13/00 ,  H04L12/56 ,  H04L13/08 ,  H04L29/08

Abstract: PROBLEM TO BE SOLVED: To reduce the overhead regarding the use of descriptors and descriptor rings relating to respective frame data buffers by updating only the starting and ending descriptors in a descriptor chain for a desired host or controller. SOLUTION: A network controller 40 updates a starting and an ending descriptor entry which are concerned to optimize the use of a bus when >=3 frame data buffers are chained together. When the network controller 40 completes the process as to a buffer relating to chained frames, the possession of the ending descriptor is returned first and then the possession of the starting descriptor is returned. The flags and fields of the starting and ending descriptors in a column type chain of a fence post, i.e., a fence are all updated by the controller 40 and when they are completely sent or received, accurate information regarding the frames is provided.

公开(公告)号：JP2000165455A

公开(公告)日：2000-06-16

申请号：JP27823599

申请日：1999-09-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHRISTIAN D CASPER

IPC: G06F5/06 ,  G06F13/12 ,  G06F13/14 ,  G06F13/20 ,  G06F13/28 ,  G06F13/32 ,  H04L12/56 ,  H04L13/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for using a look-ahead watermark in an FIFO memory and to provide a network system. SOLUTION: In the case that data in an FIFO memory exceeds a watermark threshold value, the FIFO memory generates a watermark interruption. A data burst is transferred to the FIFO memory via a direct memory access unit. In the case that a look-ahead watermark flag indicates that a sufficient memory space is available, the FIFO memory checks the look-ahead watermark flag in order to decide whether or not a sufficient memory space is in existence in the FIFO memory for an additional data burst transferred to the FIFO memory via the direct memory access unit.

公开(公告)号：JP2000115252A

公开(公告)日：2000-04-21

申请号：JP27883399

申请日：1999-09-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHRISTIAN D CASPER ,  ELMER H GRITS

IPC: H04L13/08 ,  H04L12/56 ,  H04L12/40

Abstract: PROBLEM TO BE SOLVED: To reduce congestion and frame loss of a port receiver by aborting an inputted frame by which frame overflow is generated in a FIFO memory. SOLUTION: Four network controllers 40 are connected with a 32 bit system bus which is connected with a host system 43. A host microprocessor 44 is connected with a system bus 42 as well as a common memory sub-system 46. A status error indicator in a reception FIFO memory to indicate the frame overflow in the FIFO memory is generated. An early stage congestion interrupt is generated from the FIFO memory to a communication processor after generation of the status error indicator. Furthermore, an instruction is generated from the host processor 44 to the FIFO memory to abort the inputted frame by which the frame overflow is generated. And the number of words of burst dimension of a memory access unit is directly increased or time slice of other active process is corrected.