公开(公告)号：JP2001349911A

公开(公告)日：2001-12-21

申请号：JP2001085086

申请日：2001-03-23

Applicant: ST MICROELECTRONICS INC

Inventor： ELLIOT WILLIAM D

IPC: G01R25/00 ,  G02F1/133 ,  G06F1/04 ,  G09G3/20 ,  G09G5/00 ,  H03K5/26 ,  H03L7/06 ,  H03L7/081 ,  H03L7/085 ,  H04N5/12 ,  H04N5/66

Abstract: PROBLEM TO BE SOLVED: To provide a technology of measuring the phase difference between synchronous signals with high accuracy. SOLUTION: This system has an integrated circuit device for comparing the relative phases of first and second signals with each other with very high accuracy. This system has a first input for receiving the first signal provided with a first edge and a second input for receiving the second signal provided with a second edge. A first delay chain has at least one first delay element, and a second delay chain has at least one second delay element. At least one symmetric flip flop has the first and second inputs connected to each output tap of the first and second delay elements, and the output of the flip flop indicates which of the first and second edges reaches the first and second inputs first.

公开(公告)号：JP2001326830A

公开(公告)日：2001-11-22

申请号：JP2001085624

申请日：2001-03-23

Applicant: ST MICROELECTRONICS INC

Inventor： ELLIOT WILLIAM D ,  NEUGEBAUER CHARLES F

IPC: H04N5/12 ,  G09G3/20 ,  G09G5/00 ,  H03K5/00 ,  H03K5/1252 ,  H03K5/13 ,  H03L7/081 ,  H03L7/089 ,  H03L7/091

Abstract: PROBLEM TO BE SOLVED: To provide an enhanced system that employs a digital phase locked loop. SOLUTION: The system has a digital phase locked loop(PLL) consisting of a full digital circuit configuration and a standard cell structure. The digital PLL has a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including digital chains, a non-glitch MUX and a phase accumulator. The digital phase detector is electrically coupled with the digital frequency synthesizer and supplies digital code information denoting a phase error between the edge of an input reference signal and the edge of a synthesized signal by comparing the edge of the input reference signal with the edge of the synthesized signal.