公开(公告)号：DE69425636D1

公开(公告)日：2000-09-28

申请号：DE69425636

申请日：1994-11-17

Applicant: ST MICROELECTRONICS INC

Inventor： KALNITSKY ALEX ,  LIN YIH-SHUNG

IPC: H01L21/3105 ,  H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer (1) of spin-on glass is deposited, a layer of low-temperature oxide (3) is deposited before a second layer of spin-on glass (2).

公开(公告)号：DE69425636T2

公开(公告)日：2001-01-25

申请号：DE69425636

申请日：1994-11-17

Applicant: ST MICROELECTRONICS INC

Inventor： KALNITSKY ALEX ,  LIN YIH-SHUNG

IPC: H01L21/3105 ,  H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer (1) of spin-on glass is deposited, a layer of low-temperature oxide (3) is deposited before a second layer of spin-on glass (2).