公开(公告)号：JP2000137613A

公开(公告)日：2000-05-16

申请号：JP30471099

申请日：1999-10-26

Applicant: ST MICROELECTRONICS INC

Inventor： NARESH H SONI

IPC: G06F9/32 ,  G06F9/00 ,  G06F9/06 ,  G06F9/318 ,  G06F13/16 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To improve the speed and efficiency of a microprocessor while maintaining the interchangeability of instruction set architectures. SOLUTION: A virtual condition code(VCC) for controlling an instruction sequence in a microprocessor is used. The virtual condition code is not controlled by a programmer, and stored in an inside non-architecture type register to be used by various kinds of microprocessor instruction for deciding when branching should be operated. For example, the virtual condition code can be used as a condition for operation branching from a series or repeated instructions. The virtual condition makes it possible to remove one part of overhead on processing to be used at the time of deciding whether or not successive digits such as count values in the register are 0 related with the repeated instructions of a loop or the like.

公开(公告)号：JP2000105699A

公开(公告)日：2000-04-11

申请号：JP24550499

申请日：1999-08-31

Applicant: ST MICROELECTRONICS INC

Inventor： NARESH H SONI

IPC: G06F9/38 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To improve the parallelism in data processing, to decrease the time for waiting the execution of instruction and to accelerate the processing speed. SOLUTION: A data processing system having distributed reservation stations 50-53 is provided and this distributed reservation stations 50-53 store the basic blocks of codes in the format of a microprocessor instruction. Accordingly, the basic block of the code can be distributed to several distributed reservation stations 50-53. Thus, the number of entries in each of distributed reservation stations 50-53 can be decreased, the duration for executing the instruction is reduced and the processing speed is accelerated.

公开(公告)号：JPH11316680A

公开(公告)日：1999-11-16

申请号：JP37367598

申请日：1998-12-28

Applicant: ST MICROELECTRONICS INC

Inventor： NARESH H SONI ,  DAVID ISAAMAN

IPC: G06F7/00 ,  G06F9/34 ,  G06F9/42 ,  G06F9/46 ,  G06F13/32

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for decreasing the waiting time related to the preservation and storage of the state of a floating point register in a microprocessor at the time of switching between floating point operation and MMX operation. SOLUTION: In a CPU, a secondary register file is maintained together with a primary floating point register file. When task switching to MMX or to another context occurs, the primary register keeps the state of a floating point task 'as it is'. The address of a domain to preserve the state of an FPU 20 is maintained in a preservation domain address register. Next, the secondary register is utilized for the other context in order to store the result of the executed instruction. When switching to floating point operation occurs in many cases, the previous state is recovered from the primary register without generating any waiting time for retrieving instructions and data from a memory subsystem.