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    HIGH SPEED MULTIPLIER
    1.
    发明专利
    HIGH SPEED MULTIPLIER 失效

    公开(公告)号：JP2000112714A

    公开(公告)日：2000-04-21

    申请号：JP27892599

    申请日：1999-09-30

    Applicant: ST MICROELECTRONICS INC

    Inventor： NGUYEN THI N

    IPC: G06F7/52 ,  G06F7/523 ,  G06F7/544

    Abstract: PROBLEM TO BE SOLVED: To reduce the repeat of multiplication and also execute accelerated multiplication by comparing the cache look-up bit of a multiplicand with a preceding multiplicand. SOLUTION: A multiplier circuit 306 performs an operation about a multiplicand 302 and a multiplier 304. The multiplier 304 is designated as a constant and an output is supplied onto a line 308. When required number repeat takes place, a data effective line 310, for instance, shows a clear value such as true and when the value is detected, a result on the line 308 becomes a final product. The multiplicand is divided into a cache look-up bit(CLB) part and a table look-up bit(TLB) part. For sequential multiplicands, values are close to each other, the CLB part does not change, what is more important is that the CLB part of the product does not change and this fact enables the number of repeats which is needed to reach a final product to be reduced.

    FLOATING GATE ASSOCIATIVE STORAGE DEVICE
    2.
    发明专利
    FLOATING GATE ASSOCIATIVE STORAGE DEVICE 失效

    公开(公告)号：JP2000187991A

    公开(公告)日：2000-07-04

    申请号：JP35643599

    申请日：1999-12-15

    Applicant: ST MICROELECTRONICS INC

    Inventor： CHAN TSIU CHIU ,  NGUYEN THI N

    IPC: G11C17/00 ,  G11C15/04

    Abstract: PROBLEM TO BE SOLVED: To enable data storage inside a non-volatile associative storage device by making a storage device operable to connect a bit line to an output terminal if the first data bit has first logical level, and making the device operable to connect a complementary bit line to an output terminal if the first data bit has second logical state. SOLUTION: If the first input/output 13 is connected to the ground through a floating gate transistor 12, a CAM cell 10 is such that a transistor 28 connects a complementary bit line 30 to a transistor 32. The logic 'o' of the first input/ output 13 is applied to the gate of the transistors 26, 28, turning off the transistor 26, and connecting the complementary bit line 30 to the gate of the transistor 32. In the case where the data bit to be applied to the bit line 20 matches the data value to be stored in the transistor 12, the data bit to the complementary bit line turns on the transistor 32 and grounds a match line 34.

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