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1.发明专利
公开(公告)号：JP2003109334A
公开(公告)日：2003-04-11
申请号：JP2002187246
申请日：2002-06-27
Applicant: ST MICROELECTRONICS INC
Inventor： HEYDARI FEREIDOON , OZDEMIR HAKAN , ARF SADIK O
Abstract: PROBLEM TO BE SOLVED: To provide a servo circuit containing a synchronous servo channel and a method for synchronously restoring servo data from a data storage disk. SOLUTION: A new synchronous Partial Response Maximum Likelihood (PRML) servo is provided for a high track-per-inch disk-drive system. To increase data capacity in hard disk drives (HDD), one can shorten a servo format and/or increase track density. This servo system has circuits that allow a high-performance and accurate system for positioning read-write heads. Major circuits include burst demodulation, Viterbi detection, timing synchronization, and spin-up search. A highly linear discrete-fourier-transform (DFT) burst demodulation circuit can demodulate high-density and low-signal-to-noise-ratio (SNR) position bursts.
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2.发明专利
公开(公告)号：JP2001273720A
公开(公告)日：2001-10-05
申请号：JP2001037421
申请日：2001-02-14
Applicant: ST MICROELECTRONICS INC
Inventor： OZDEMIR HAKAN , BYRNE JASON D
Abstract: PROBLEM TO BE SOLVED: To provide improved technology to determine the phase difference between a sample clock and sampled signals. SOLUTION: The circuit is provided with a buffer which receives two sampled signals and stores the signals and a phase computing circuit which computes the phase difference between one of the sampled signals and a prescribed point of the signals. The circuit is used to reduce matching obtaining time of a digital timing recovery loop. Thus, the use of the circuit makes it possible to reduce sector preamble and also to increase the data storage density of a disk. In one embodiment, the circuit is used to determine an initial phase difference between disk drive reading signals and a reading sample clock. The digital timing recovery loop provides an initial coarse matching between read signals and a sample clock by using the phase difference. By giving the initial coarse matching, the recovery loop reduces overall matching obtaining time.
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公开(公告)号：JP2003100030A
公开(公告)日：2003-04-04
申请号：JP2002187783
申请日：2002-06-27
Applicant: ST MICROELECTRONICS INC
Inventor： HEYDARI FEREIDOON , OZDEMIR HAKAN
Abstract: PROBLEM TO BE SOLVED: To provide an enhanced technology for encoding servo data on a data storage disk. SOLUTION: This invention incorporates a 1/4-rate Hard Disk Drive (HDD) servo-data encoding into a Partial Response Maximum Likelihood (PRML) read channel. The data is read back (or sampled) at twice the write frequency. This increases the data redundancy while also increasing the data density and the disk storage capacity. The 1/4 coding can also be applied to conventional HDD dibit coding. Specifically, the 1/4-coding scheme reads each dibit-coded servo data transition 01 as 0011, and reads each non-transition 00 (or 0) as 0000. The 1/4 coding and its matched Viterbi detector can also increase the data detection in comparison to conventional peak-detection schemes.
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公开(公告)号：JP2001283527A
公开(公告)日：2001-10-12
申请号：JP2001036348
申请日：2001-02-14
Applicant: ST MICROELECTRONICS INC
Inventor： OZDEMIR HAKAN
Abstract: PROBLEM TO BE SOLVED: To increase the storage capacity of a recording medium by making preambles used on the recording medium short. SOLUTION: The circuit which controls the gain of an amplifier amplifying an information signal has two buffers for storing two samples of the amplified information signal and also has a gain determining circuit coupled with the buffers. This gain determining circuit generates gain control for shifting the amplitude of the information signal amplified by the amplifier according to the two samples to or toward a specific amplitude. This circuit is able to give initial rough gain control to a read signal amplifier for a disk drive read channel. This initial control accelerates the more speedy stabilization of the amplifier gain in the beginning of a data sector and the speeded-up stabilization allows the data sector to have a shorter preamble, so that a disk can have higher data storage density.
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公开(公告)号：JP2001148169A
公开(公告)日：2001-05-29
申请号：JP2000298957
申请日：2000-09-29
Applicant: ST MICROELECTRONICS INC
Inventor： OZDEMIR HAKAN , REZZI FRANCESCO
Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit and a method for restoring synchronous information from a signal. SOLUTION: This synchronizing circuit has an input terminal, an output terminal, and a restoring circuit coupled to the input terminal and the output terminal. The input terminal receives an input signal having a synchronizing mark. the restoring circuit restores a synchronizing mark from the input signal and can operate, so that a synchronizing signal is generated on the output terminal responding to the restored synchronizing mark.
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Patent Agency Ranking
公开(公告)号：JP2002304820A
公开(公告)日：2002-10-18
申请号：JP2002037007
申请日：2002-02-14
Applicant: ST MICROELECTRONICS INC
Inventor： OZDEMIR HAKAN , BYRNE JASON D , HEYDARI FEREIDOON
Abstract: PROBLEM TO BE SOLVED: To provide an enhanced Viterbi detector that recovers a binary sequence from a read signal read by a disk drive system or the like. SOLUTION: This invention provides the Viterbi detector receiving a signal that represents a binary sequence having groups of no more and no fewer than a predetermined number of consecutive bits each having a first logic level, where the groups are separated from each other by respective bits having a second logic level. The Viterbi detector recovers the binary sequence from the signal by calculating a respective path metric for each of no more than four possible states of the binary sequence, and determining a surviving path from the calculated path metrics, where the binary sequence lies along the surviving path. Or the Viterbi decoder recovers the binary sequence from the signal by calculating respective path metrics for possible states of the binary sequence, calculating multiple path metrics for no more than one of the possible states, and determining the surviving path from the calculated path metrics.
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公开(公告)号：JP2001297534A
公开(公告)日：2001-10-26
申请号：JP2001036767
申请日：2001-02-14
Applicant: ST MICROELECTRONICS INC
Inventor： OZDEMIR HAKAN
Abstract: PROBLEM TO BE SOLVED: To provide a circuit and method for controlling the gain of an amplifier in accordance with the sum of the samples of amplified signals and a technique of increasing memory density by shortening the preambles recorded on a recording medium. SOLUTION: This circuit controls the gain of the amplifier which amplifies information signals. The circuit has a buffer for storing the first and second samples of the amplified information signals and a gain determining circuit coupled to these buffers. The gain determining circuit generates gain adjustment in accordance with the sum of the first and second samples. The gain adjustment changes the amplification of the information signals amplified by the amplifier to the prescribed amplification or toward the same. Such circuit can impart the initial rough gain adjustment to the reading signal amplifier in a disk drive reading channel. As compared to the conventional reading channel, this initial adjustment promotes the stabilization faster than the gain of the amplifier in the beginning of data sectors. The faster stabilization enables the data sectors to have the shorter preambles and consequently the disk can have the higher data storage (memory) density.
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公开(公告)号：JP2001291341A
公开(公告)日：2001-10-19
申请号：JP2001036455
申请日：2001-02-14
Applicant: ST MICROELECTRONICS INC
Inventor： OZDEMIR HAKAN
Abstract: PROBLEM TO BE SOLVED: To increase the memory capacity of a recording medium by shortening the preamble to be recorded on the recording medium. SOLUTION: A phase calculation circuit has a buffer, an approximation circuit and an interpolator. The buffer receives and stores the first and second samples of periodic signals having peak amplitude. This approximation circuit linearly approximates part of the periodic signals and calculates one relative phase among the samples within the signal segments. The interpolator calculates the relative phase of one sample relating to the prescribed point of the signals by using the values of the relative phase and first and second samples of the samples within the signal segments. Such circuit may be used to decrease the matching acquisition time of a digital timing restoration loop and is therefore capable of shortening the perample and increasing the data memory density of a disk.
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公开(公告)号：DE60032089D1
公开(公告)日：2007-01-11
申请号：DE60032089
申请日：2000-09-20
Applicant: ST MICROELECTRONICS INC
Inventor： REZZI FRANCESCO , OZDEMIR HAKAN
Abstract: A synchronizer circuit includes a recovery circuit coupled to the input and output terminals. The input signal includes a sync mark, and the recovery circuit is operable to recover the sync mark and generate a synchronization signal on the output terminal. Such a synchronizer circuit can recover the synchronization mark from a read signal and locate the beginning of a data stream for a separate Viterbi detector thereby reducing the complexity and increase the data-recovery speed of the Viterbi detector. The sync mark may be recovered by executing state-transition routines in alignment with the input signal.
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公开(公告)号：DE60122402D1
公开(公告)日：2006-10-05
申请号：DE60122402
申请日：2001-01-30
Applicant: ST MICROELECTRONICS INC
Inventor： OZDEMIR HAKAN , BYRNE JASON D
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