公开(公告)号：JP2001216195A

公开(公告)日：2001-08-10

申请号：JP2000397620

申请日：2000-12-27

Applicant: ST MICROELECTRONICS INC

Inventor： FLAKE LANCE LESLIE ,  TIMOTHY RICHARD FELDMANN

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a technology to specify a form of a cache to permit efficient common use of a binary dimension memory space between use of cache and use of non-cache and to access the cache. SOLUTION: A storage device with plural blocks is provided and each block is identified by a block address. A target block address is identified by an access request. The target block address consists of an upper part and a lower part. Non-binary operation is executed for the upper part and a quotient and odds are generated. Its odd part is coupled with the lower part and an index is created. The index is applied to tag memory structure and one or one set of entries in the tag memory structure are selected. The contents of the selected entries are compared with a quotient part and whether or not its target block is expressed in the cache is decided.