公开(公告)号：JP2000067580A

公开(公告)日：2000-03-03

申请号：JP23220099

申请日：1999-08-19

Applicant: ST MICROELECTRONICS INC

Inventor： BRADY JAMES ,  WORLEY JAMES L

IPC: G11C11/409 ,  G11C7/12

Abstract: PROBLEM TO BE SOLVED: To quickly and surely drive bit lines and memory cells to complete reference voltage levels by detecting electric charge appearing on a corresponding bit line pair from the reading of data from a DRAM cell and also driving the bit line pair to complete reference voltage levels Vdd/Vss. SOLUTION: When the voltage of a bit line 2 is higher a little and the voltage of a bit line 3 is lower a little as compared with a voltage Vdd/2 from the result of reading those voltages a sense amplifier reference line 18 is driven to a low reference voltage level Vss and succeedingly a recovery control line 14 is driven to a high reference voltage level Vdd. A sense amplifier 7 detects the voltage difference between nodes 15, 16 and starts to drive the nodes 15, 16 to the high reference voltage level Vdd and the low reference voltage level Vss respectively. When pass/transmission gates 8, 9 are both turned ON, bit lines 2, 3 follow up voltage levels of the nodes 15, 16 respectively. As a result, a second transistor 12 is turned ON to pull up the bit line 2 to the high reference voltage level Vdd quickly.

公开(公告)号：JP2001357695A

公开(公告)日：2001-12-26

申请号：JP2001130761

申请日：2001-04-27

Applicant: ST MICROELECTRONICS INC

Inventor： WORLEY JAMES L

IPC: G11C11/401 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM device having twist type bit line architecture in which a redundant row consisting of memory cells can be effectively used when a memory cell row has a defect. SOLUTION: A form of a pair of redundant row can be specified to replace any one of rows consisting of memory cells having defect in a redundant row decoding circuit. Each pair of bit line is integrated to a separate memory cell from each redundant row of pairs of redundant row, therefore, both of true version and complement version of a data value are kept by the pair of redundant row. A row consisting of reference cells is cut off and/or disabled during a memory access operation period related by the pair of redundant row.

公开(公告)号：DE60301683D1

公开(公告)日：2005-11-03

申请号：DE60301683

申请日：2003-03-27

Applicant: ST MICROELECTRONICS INC

Inventor： WORLEY JAMES L

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/409

Abstract: A sense amplifier (1) for use in memory devices. The sense amplifier (1) may include a pair of cross-coupled inverters (2A,2B), each inverter including at least two transistors (4,5). The sense amplifier (1) may further include a first capacitor (10) coupled to a first input/output terminal (BLC) of the sense amplifier (1) and a second capacitor (11) coupled to a second input/output terminal (BLT) thereof. A change in voltage differential appearing across the input/output terminals (BLC,BLT) bootstraps the cross-coupled inverters (2A,2B) to facilitate activation and deactivation of the transistors (4,5) in the cross-coupled inverters (2A;2B). Consequently, response time of the sense amplifier (1) is reduced.