公开(公告)号：JP2001249843A

公开(公告)日：2001-09-14

申请号：JP2000401113

申请日：2000-12-28

Applicant: ST MICROELECTRONICS INC

Inventor： CHOWDHURI BHASKAR ,  BANGA KANWAL PREET SINGH ,  PALAZZOLO FRANK JR ,  ZAMPIERI UGO

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/08 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393

Abstract: PROBLEM TO BE SOLVED: To provide technology to accelerate a graphics operation. SOLUTION: This system is provided with a memory device to accelerate the graphics operation (calculation) in electronic equipment. A memory controller is used to control pixel data to be transmitted from the memory device and to it. A cache memory is electrically coupled with the memory, a shape is specified to dynamically selected usable dimension and the quantity of the pixel data having the selected usable dimension is exchanged with the memory controller. The memory device can be defined as an SDRAM. The cache memory can be provided with plural usable memory areas or tiles.