公开(公告)号：GB2495543A

公开(公告)日：2013-04-17

申请号：GB201117766

申请日：2011-10-14

Applicant: ST MICROELECTRONICS RES & DEV

Inventor： SARTA DAVIDE ,  SMITH DAVID

IPC: G06F9/48 ,  G06F13/24

Abstract: A routing architecture for routing interrupt requests (IRQ) receives m inputs, irq_in, and outputs n output request signals, irq_out. Shift register 18 receives m inputs and is configured such that k bits are shifted down in one cycle, where m is greater than k. The k bits of shift register 18 are provided to routing arrangement or multiplexer 20, e.g. a full combinatorial k x n cross bar, which provides n outputs to an output logic register 28 comprising set logic. Routing arrangement 20 is configured to perform a plurality of cycles to provide said set of n output request signals. Shift register 18 has to be shifted m/k times, meaning that m/k cycles are required for routing arrangement 20 to produce n outputs. Accordingly, instead of a large routing arrangement in one step, a smaller routing arrangement 20 is used a plurality of times. The routing architecture also includes, inverters 10, mask 12, synchronisation register 14 and a controller FSM (finite state machine) 26. The invention may be used with any suitable requests, e.g. direct memory access (DMA) requests, status requests, and/or service requests.