公开(公告)号：EP2240956B1

公开(公告)日：2013-08-21

申请号：EP08869950.9

申请日：2008-12-31

Applicant: ST Microelectronics (Rousset) SAS

Inventor： FORNARA, Pascal

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  G04F10/10 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C27/00 ,  H01L29/66 ,  H01L21/8247 ,  H01L27/115

CPC classification number: G04F10/10 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/349 ,  G11C27/005 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

公开(公告)号：EP2286450B1

公开(公告)日：2011-10-19

申请号：EP09757723.3

申请日：2009-05-12

Applicant: ST Microelectronics (Rousset) SAS

Inventor： FORNARA, Pascal

IPC: H01L21/8246 ,  H01L27/02 ,  H01L27/112 ,  H01L27/115 ,  G11C16/00 ,  G11C17/00

CPC classification number: H01L27/1052 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11519 ,  H01L27/11521

Abstract: A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.

公开(公告)号：EP2240956A1

公开(公告)日：2010-10-20

申请号：EP08869950.9

申请日：2008-12-31

Applicant: ST Microelectronics (Rousset) SAS

Inventor： FORNARA, Pascal

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  G04F10/10 ,  G11C16/04 ,  H01L29/423 ,  H01L29/51

CPC classification number: G04F10/10 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/349 ,  G11C27/005 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: The invention relates to an EEPROM memory cell that comprises a dual-gate MOS transistor in which the two gates (87, 98) are separated by an insulation layer, characterised in that the insulation layer includes a first portion (89) and a second portion (96) having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor.

公开(公告)号：EP2286450A1

公开(公告)日：2011-02-23

申请号：EP09757723.3

申请日：2009-05-12

Applicant: ST Microelectronics (Rousset) SAS

Inventor： FORNARA, Pascal

IPC: H01L21/8246 ,  H01L27/02 ,  H01L27/112 ,  H01L27/115 ,  G11C16/00 ,  G11C17/00

CPC classification number: H01L27/1052 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11519 ,  H01L27/11521

Abstract: A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.

Abstract translation: 一种非易失性存储器，至少包括第一和第二存储单元，每个存储单元包括具有双栅极的存储MOS晶体管和设置在两个栅极之间的绝缘层。 第二存储器单元的存储晶体管的绝缘层包括绝缘层比第一存储器单元的存储晶体管的绝缘层更少的至少一个部分。