公开(公告)号：US20030080789A1

公开(公告)日：2003-05-01

申请号：US10237260

申请日：2002-09-06

Applicant: ST Microelectronics S.A.

Inventor： Joel Caranana

IPC: H03B001/00

CPC classification number: H03K19/01707 ,  G06F13/4077 ,  H03K5/151 ,  H03K19/00323

Abstract: A bus interface having a first circuit based on a first pair of transistors of opposite types having a control electrode and a common electrode for providing a first output potential. A second circuit has a second pair of transistors of opposite types and having a common electrode for providing a second potential switching in opposite direction from the former. This device has a first capacitive coupling means for feeding a portion of the signal existing at said first potential back into said control electrode of said second transistor pair and second capacitive coupling means for feeding a portion of the signal existing at said second potential back into said control electrodes of said first transistor pair. Thus variations between the rise and decay times of the transistors of each pair can be compensated for.

Abstract translation: 一种总线接口，具有基于相反类型的第一对晶体管的第一电路，具有用于提供第一输出电位的控制电极和公共电极。 第二电路具有相反类型的第二对晶体管，并具有用于提供与前者相反方向的第二电位切换的公共电极。 该装置具有第一电容耦合装置，用于将存在于所述第一电位的信号的一部分馈送到所述第二晶体管对的所述控制电极中;以及第二电容耦合装置，用于将存在于所述第二电位的信号的一部分馈送到所述第二电容耦合装置， 所述第一晶体管对的控制电极。 因此，可以补偿每对晶体管的上升和衰减时间之间的变化。