MOSFET DEVICE WITH HIGH INTEGRATION DENSITY, IN PARTICULAR POWER VDMOS, AND MANUFACTURING PROCESS THEREOF
    1.
    发明申请
    MOSFET DEVICE WITH HIGH INTEGRATION DENSITY, IN PARTICULAR POWER VDMOS, AND MANUFACTURING PROCESS THEREOF 审中-公开
    具有高集成密度,特殊功率VDMOS的MOSFET器件及其制造工艺

    公开(公告)号:WO2006122957A2

    公开(公告)日:2006-11-23

    申请号:PCT/EP2006/062394

    申请日:2006-05-17

    Inventor: CURRO', Giuseppe

    Abstract: MOSFET device formed in a semiconductor layer (12) overlaid by an insulated-gate structure (13, 14, 21) having at least two gate electrodes (14), of semiconductor material, which extend at a distance from one another and delimit between them a strip-shaped opening (15). The semiconductor layer accommodates a strip-shaped body region (19), which in turn accommodates a source region (20). A source-contact metal region (29) extends at least partially in the opening (15) and is in electrical contact with the body region (19) and the source structure (20, 25). The opening (15) is formed by elongated windows (15a) and contact cells (18) extending between pairs of consecutive elongated windows. The elongated windows (15) are filled with dielectric spacer material (26), and the metal contact structure (29) has first portions extending above the opening (15) at the elongated windows (15a) and second portions extending within the opening at the contact cells (18) and in direct electrical contact with the source structure (20, 25).

    Abstract translation: MOSFET器件形成在由绝缘栅结构(13,14,21)重叠的半导体层(12)中,所述绝缘栅极结构(13,14,21)具有半导体材料的至少两个栅电极(14),它们彼此间隔开并在它们之间限定 带状开口(15)。 半导体层容纳条形体区域(19),其又容纳源区域(20)。 源极接触金属区域(29)至少部分地延伸在开口(15)中并且与体区域(19)和源结构(20,25)电接触。 开口(15)由细长的窗口(15a)和在成对的连续细长窗口之间延伸的接触单元(18)形成。 细长的窗口(15)填充有介电隔离材料(26),并且金属接触结构(29)具有在细长窗口(15a)处在开口(15)上方延伸的第一部分,并且在开口 接触电池(18)并与源结构(20,25)直接电接触。

    PROCESS FOR MANUFACTURING A MOS DEVICE WITH INTERCELL ION IMPLANT
    2.
    发明申请
    PROCESS FOR MANUFACTURING A MOS DEVICE WITH INTERCELL ION IMPLANT 审中-公开
    用于制造具有INTERCELL离子植入物的MOS器件的方法

    公开(公告)号:WO2006114376A1

    公开(公告)日:2006-11-02

    申请号:PCT/EP2006/061664

    申请日:2006-04-19

    Inventor: CURRO', Giuseppe

    Abstract: In a process for manufacturing a MOS device: forming a semiconductor layer (23) having a first type of conductivity; forming an insulated gate structure (27) having an electrode region (25), above the semiconductor layer (23); forming body regions (37) having a second type of conductivity, within the semiconductor layer (23), laterally and partially underneath the insulated gate structure (27); forming source regions (38) having the first type of conductivity, within the body regions (37); and forming a first enrichment region (42), in a surface portion of the semiconductor layer (23) underneath the insulated gate structure (27), the first enrichment region (42) having the first type of conductivity and being set at a distance from 10 the body regions (37). In order to form the first enrichment region (42), a first enrichment window (30) is defined within the insulated gate structure (27), and first dopant species of the first type of conductivity are introduced through the first enrichment window (30) and in a way self-aligned thereto.

    Abstract translation: 在制造MOS器件的工艺中:形成具有第一类导电性的半导体层(23); 在所述半导体层(23)的上方形成具有电极区域(25)的绝缘栅极结构(27)。 在所述半导体层(23)内形成具有第二导电类型的主体区域(37),在所述绝缘栅极结构(27)的横向和部分下方。 在体区(37)内形成具有第一类导电性的源区(38); 以及在所述绝缘栅极结构(27)下方的所述半导体层(23)的表面部分中形成第一富集区域(42),所述第一富集区域(42)具有所述第一类型的导电性并且被设置为距离 10身体区域(37)。 为了形成第一富集区域(42),在绝缘栅极结构(27)内限定第一富集窗口(30),并且通过第一富集窗口(30)引入第一类型的导电性的第一掺杂物质, 并以其自身对准的方式。

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