公开(公告)号：EP3040888A2

公开(公告)日：2016-07-06

申请号：EP15190240.0

申请日：2015-10-16

Applicant: STMicroelectronics, Inc.

Inventor： BISHT, Chetan ,  SCRIVENER III, Harry

IPC: G06F17/50 ,  H01L27/00

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H03F3/195 ,  H03F3/602 ,  H03K19/017509

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

Abstract translation: 集成电路片上系统（SOC）包括半导体衬底，由形成在衬底中的晶体管构成的多个部件，以及在组件之间提供电连接的多个互连线。 使用无通道设计消除了芯片顶表面上的互连通道。 相反，互连线在金属化的顶层中彼此邻接，从而保留了5-10％的芯片不动产。 通常沿组件之间的互连通道定位的时钟缓冲器位于包含组件的衬底的区域内。 无通道集成电路的设计规则允许馈通互连并排除多扇出互连。

公开(公告)号：EP3040888A3

公开(公告)日：2016-12-28

申请号：EP15190240.0

申请日：2015-10-16

Applicant: STMicroelectronics, Inc.

Inventor： BISHT, Chetan ,  SCRIVENER III, Harry

IPC: G06F17/50 ,  H01L27/00 ,  H03K19/0175

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H03F3/195 ,  H03F3/602 ,  H03K19/017509

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

Abstract translation: 集成电路片上系统（SOC）包括半导体衬底，由在衬底中形成的晶体管构成的多个部件以及在部件之间提供电连接的多条互连线。 使用无通道设计消除了芯片顶部表面上的互连通道。 取而代之的是，互连线在顶层金属化层中彼此邻接，因此保留了5-10％的芯片面积。 典型地沿着部件之间的互连通道定位的时钟缓冲器相反位于包含部件的衬底的区域内。 无通道集成电路的设计规则允许馈通互连并排除多扇出互连。