公开(公告)号：EP0915616A1

公开(公告)日：1999-05-12

申请号：EP98308775.0

申请日：1998-10-27

Applicant: STMicroelectronics, Inc.

Inventor： Guerrieri, Roberto ,  Rambaldi, Roberto ,  Tartagni, Marco

IPC: H04N3/15

CPC classification number: H01L27/14609 ,  H04N5/363 ,  H04N5/374 ,  H04N5/3745

Abstract: Disclosed is a method and associated apparatus for compensating for kTC noise in individual pixels of an MOS imaging array. The kTC noise at issue forms when a pixel is disconnected from a reset voltage by turning off an MOS transistor which controls access to the pixel photodiode. Compensation is accomplished by first exposing the photodiode to the reset voltage and then disconnecting the well region from V dd to cause it to float. By allowing the well to float, the kTC charge subsequently introduced (at the conclusion of the reset process) redistributes so that most of it accumulates on the capacitor between the well and the substrate. Later, the well is reclamped to V dd , and the noise contribution stored in the well-substrate capacitor is canceled. A disclosed apparatus includes an array of pixels, each having a separate well. In addition, access of the well to a source of power (V dd ) must be switchable. Therefore, a transistor is included at each pixel's connection to a V dd .

Abstract translation: 公开了用于补偿MOS成像阵列的各个像素中的kTC噪声的方法和相关装置。 通过关闭控制对像素光电二极管的访问的MOS晶体管，当像素与复位电压断开时，形成所讨论的kTC噪声。 通过首先将光电二极管暴露于​​复位电压，然后将阱区域与Vdd断开以使其浮动来实现补偿。 通过允许阱浮动，随后引入的kTC电荷（在复位过程结束时）重新分布，使得其大部分积聚在阱和衬底之间的电容器上。 之后，井改为Vdd，并且消除了存储在阱底板电容器中的噪声贡献。 公开的装置包括像素阵列，每个像素阵列具有单独的孔。 此外，井到电源（Vdd）的访问必须是可切换的。 因此，在每个像素与Vdd的连接处包括晶体管。

公开(公告)号：EP0915518A3

公开(公告)日：2001-01-10

申请号：EP98308776.8

申请日：1998-10-27

Applicant: STMicroelectronics, Inc.

Inventor： Guerrieri, Roberto ,  Bisio, Marco ,  Tartagni, Marco

IPC: H01L27/146 ,  H04N3/15 ,  H04N5/217

CPC classification number: H04N5/378 ,  G11C5/063 ,  G11C7/06 ,  H04N5/357 ,  H04N5/3742

Abstract: A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

公开(公告)号：EP0915518A2

公开(公告)日：1999-05-12

申请号：EP98308776.8

申请日：1998-10-27

Applicant: STMicroelectronics, Inc.

Inventor： Guerrieri, Roberto ,  Bisio, Marco ,  Tartagni, Marco

IPC: H01L27/146 ,  H04N3/15

CPC classification number: H04N5/378 ,  G11C5/063 ,  G11C7/06 ,  H04N5/357 ,  H04N5/3742

Abstract: A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

Abstract translation: 描述了一种电路技术，以减少电荷积分器的输入电容线。 这种方法特别适合用于在固态集成传感器嵌入读出电路。 在描述的集成电荷放大器包括通用放大器元件和驱动放置在输入线下面的金属屏蔽一个高速缓冲。 金属屏蔽THEREFORE跟随输入线的电势，从而减少输入线和接地之间的电容。