公开(公告)号：EP1235139B1

公开(公告)日：2009-12-16

申请号：EP01310602.6

申请日：2001-12-19

Applicant: STMicroelectronics, Inc.

Inventor： Homewood, Marc Owen ,  Jarvis, Anthony X ,  Starr, Alexander J

IPC: G06F9/38

CPC classification number: G06F9/3891 ,  G06F9/3865 ,  G06F9/3885

公开(公告)号：EP1220090A1

公开(公告)日：2002-07-03

申请号：EP01309872.8

申请日：2001-11-23

Applicant: STMicroelectronics, Inc.

Inventor： Jarvis, Anthony X

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0888 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3861 ,  G06F12/0859

Abstract: There is disclosed a data processor for stalling the instruction execution pipeline after a cache miss and re-loading the correct cache data into any bypass devices before restarting the pipeline. The data processor comprises: 1) an instruction execution pipeline comprising N processing stages, each of the N processing stages performing one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; 2) a data cache for storing data values used by the pending instruction; 3) a plurality of architectural registers for receiving the data values from the data cache; 4) bypass circuitry for transferring a first data value from the data cache directly to a functional unit in one of the N processing stages without first storing the first data value in a destination one of the plurality of architectural registers; and 5) a cache refill controller for detecting that a cache miss has occurred at a first address associated with the first data value, receiving a missed cache line from a main memory coupled to the data processor, and causing the first data value to be transferred from the missed cache line to the functional unit.

Abstract translation: 公开了一种数据处理器，用于在高速缓存未命中之后停止指令执行流水线，并在重新启动流水线之前将正确的高速缓存数据重新加载到任何旁路设备中。 数据处理器包括：1）包括N个处理级的指令执行流水线，N个处理阶段中的每一个执行与由指令执行流水线执行的待决指令相关联的多个执行步骤之一; 2）用于存储待决指令使用的数据值的数据高速缓存; 3）多个架构寄存器，用于从数据高速缓存接收数据值; 4）旁路电路，用于将第一数据值从数据高速缓存直接传送到N个处理阶段之一中的功能单元，而不首先将第一数据值存储在多个架构寄存器的目的地中; 以及5）用于检测在与所述第一数据值相关联的第一地址处发生高速缓存未命中的高速缓存补充控制器，从耦合到所述数据处理器的主存储器接收错过的高速缓存行，并且使所述第一数据值被传送 从错过的高速缓存行到功能单元。

公开(公告)号：EP1235139A3

公开(公告)日：2002-11-13

申请号：EP01310602.6

申请日：2001-12-19

Applicant: STMicroelectronics, Inc.

Inventor： Homewood, Marc Owen ,  Jarvis, Anthony X ,  Starr, Alexander J

IPC: G06F9/38

CPC classification number: G06F9/3891 ,  G06F9/3865 ,  G06F9/3885

Abstract: There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters and an interrupt and exception controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The interrupt and exception controller operates to (i) detect an exception condition associated with one of the executing instructions, wherein this executing instruction issued at time t 0 , and (ii) generate an exception in response to the exception condition upon completed execution of earlier ones of the executing instructions, these earlier executing instructions issued at time preceding t 0 .

Abstract translation: 公开了一种具有包括多个集群以及中断和异常控制器的集群架构的数据处理器。 每个簇包括具有N个处理阶段的指令执行流水线。 N个处理阶段中的每一个能够执行与由群集执行的指令相关联的多个执行步骤中的至少一个。 中断和异常控制器用于（i）检测与其中一个执行指令相关联的异常情况，其中在时间t0发出该执行指令，并且（ii）响应于异常情况在完成执行早期指令时产生异常 在执行指令中，这些在t0之前的时间发出的早期执行指令。

公开(公告)号：EP1235139A2

公开(公告)日：2002-08-28

申请号：EP01310602.6

申请日：2001-12-19

Applicant: STMicroelectronics, Inc.

Inventor： Homewood, Marc Owen ,  Jarvis, Anthony X ,  Starr, Alexander J

IPC: G06F9/38

CPC classification number: G06F9/3891 ,  G06F9/3865 ,  G06F9/3885

Abstract: There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters and an interrupt and exception controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The interrupt and exception controller operates to (i) detect an exception condition associated with one of the executing instructions, wherein this executing instruction issued at time t 0 , and (ii) generate an exception in response to the exception condition upon completed execution of earlier ones of the executing instructions, these earlier executing instructions issued at time preceding t 0 .

Abstract translation: 有游离缺失盘具有集群架构确实包括簇的多个部分并加以中断和异常控制器的数据处理器。 每个群集包括具有N个处理级指令执行管线的。 每个所述N个处理阶段的能够执行的指令与由所述执行的集群相关联的执行步骤的多个中的至少一个。 中断和异常控制器操作于（i）检测在与所述执行指令的一个相关联的异常状态，worin在时间t0发出此执行指令，以及（ii）在后早期的完成执行响应于所述异常条件的异常产生 的执行指令，论文早些时候执行在时间t0 preceding-发出的指令。