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1.发明公开Branch fetch architecture for reducing branch penalty without branch prediction 审中-公开Verzweigungsabholarchitektur zur Reduzierung von Verzweigungszeitstrafen ohne Verzweigungsvorhersage
公开(公告)号：EP1280052A2
公开(公告)日：2003-01-29
申请号：EP02254954.7
申请日：2002-07-15
Applicant: STMicroelectronics, Inc.
Inventor： Karim, Faraydon O. , Chandra, Ramesh
IPC: G06F9/38
CPC classification number: G06F9/3804 , G06F9/3842
Abstract: In lieu of branch prediction, a merged fetch-branch unit operates in parallel with the decode unit within a processor. Upon detection of a branch instruction within a group of one or more fetched instructions, any instructions preceding the branch are marked- regular instructions, the branch instruction is marked as such, and any instructions following branch are marked sequential instructions. Within two cycles, sequential instructions following the last fetched instruction are retrieved and marked, target instructions beginning at the branch target address are retrieved and marked, and the branch is resolved. Either the sequential or target instructions are then dropped depending on the branch resolution, incurring a fixed, 1 cycle branch penalty.
Abstract translation: 代替分支预测，合并的分支单元与处理器内的解码单元并行操作。 在检测到一个或多个获取的指令的组内的分支指令时，分支之前的任何指令都是标记规则的指令，分支指令被标记为这样，并且分支之后的任何指令被标记为顺序指令。 在两个周期内，检索并标记最后取出的指令之后的顺序指令，检索并标记从分支目标地址开始的目标指令，并解析分支。 然后根据分支分辨率，顺序或目标指令被丢弃，产生固定的1个循环分支罚分。
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Patent Agency Ranking2.发明公开Processor system with a plurality of processor cores for executing tasks sequentially or in parallel 有权处理器系统具有用于任务的顺序或并行执行多个核
公开(公告)号：EP1416377A1
公开(公告)日：2004-05-06
申请号：EP03256839.6
申请日：2003-10-29
Applicant: STMicroelectronics, Inc.
Inventor： Karim, Faraydon O.
CPC classification number: G06F9/4843 , G06F9/30098 , G06F9/3851
Abstract: A hyperprocessor includes a control processor controlling tasks executed by a plurality of processor cores, each of which may include multiple execution units, or special hardware units. The control processor schedules tasks according to control threads for the tasks created during compilation and comprising a hardware context including register files, a program counter and status bits for the respective task. The tasks are dispatched to the processor cores or special hardware units for parallel, sequential, out-of-order or speculative execution. A universal register file contains data to be operated on by the task, and an interconnect couples at least the processor cores or special hardware units to each other and to the universal register file, allowing each node to communicate with any other node.
Abstract translation: 该系统具有与处理器内核或特殊硬件单元，用于执行任务的多个专用处理单元。 控制处理器控制任务由处理器内核或特殊硬件单元执行的。 任务调度器通过控制处理器调度任务处理器内核或特殊硬件单元，gemäß调度。 用于执行任务的通用寄存器文件存储数据。 因此独立权利要求中包括了以下内容：（1）嵌入的处理系统; 和（2）程序执行方法。
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3.发明授权A system independent and scalable packet buffer management architecture for network processors 有权独立于系统的可扩展的包缓冲器管理体系结构的网络处理器
公开(公告)号：EP1324566B1
公开(公告)日：2009-11-11
申请号：EP02258959.2
申请日：2002-12-24
Applicant: STMicroelectronics, Inc.
Inventor： Karim, Faraydon O. , Chandra, Ramesh , Stramm, Bernd H.
IPC: H04L29/06
CPC classification number: H04L49/9031 , H04L49/90 , H04L49/901
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4.发明公开A system independent and scalable packet buffer management architecture for network processors 有权Einesystemunabhängigeskalierbare packetpufferverwaltung ArchitekturfürNetzwerkprozessoren
公开(公告)号：EP1324566A1
公开(公告)日：2003-07-02
申请号：EP02258959.2
申请日：2002-12-24
Applicant: STMicroelectronics, Inc.
Inventor： Karim, Faraydon O. , Chandra, Ramesh , Stramm, Bernd H.
IPC: H04L29/06
CPC classification number: H04L49/9031 , H04L49/90 , H04L49/901
Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.
Abstract translation: 存储用于由一个或多个网络处理器处理的分组的循环缓冲器使用空缓冲器地址寄存器来识别应该存储下一个接收到的分组的位置，下一个分组地址寄存器标识下一个待处理分组，以及一个分组处理地址寄存器 每个网络处理器识别由该网络处理器正在处理的分组。 通过软件将缓冲区的n位地址映射或掩蔽到m位数据包处理地址寄存器，从而允许缓冲区大小完全可扩展。 由网络处理器支持的专用分组检索指令检索用于使用下一个分组地址寄存器进行处理的新分组，并将其复制到相关的分组处理地址寄存器中以用于随后的访问。 因此，缓冲区管理与网络处理器架构无关。
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5.发明授权Processor system with a plurality of processor cores for executing tasks sequentially or in parallel 有权处理器系统具有用于任务的顺序或并行执行多个核
公开(公告)号：EP1416377B1
公开(公告)日：2008-08-06
申请号：EP03256839.6
申请日：2003-10-29
Applicant: STMicroelectronics, Inc.
Inventor： Karim, Faraydon O.
CPC classification number: G06F9/4843 , G06F9/30098 , G06F9/3851
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6.发明公开Branch fetch architecture for reducing branch penalty without branch prediction 审中-公开科回升架构以减少分支惩罚没有分支预测
公开(公告)号：EP1280052A3
公开(公告)日：2003-04-09
申请号：EP02254954.7
申请日：2002-07-15
Applicant: STMicroelectronics, Inc.
Inventor： Karim, Faraydon O. , Chandra, Ramesh
IPC: G06F9/38
CPC classification number: G06F9/3804 , G06F9/3842
Abstract: In lieu of branch prediction, a merged fetch-branch unit operates in parallel with the decode unit within a processor. Upon detection of a branch instruction within a group of one or more fetched instructions, any instructions preceding the branch are marked- regular instructions, the branch instruction is marked as such, and any instructions following branch are marked sequential instructions. Within two cycles, sequential instructions following the last fetched instruction are retrieved and marked, target instructions beginning at the branch target address are retrieved and marked, and the branch is resolved. Either the sequential or target instructions are then dropped depending on the branch resolution, incurring a fixed, 1 cycle branch penalty.
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